VREF ± VOS" />
參數(shù)資料
型號(hào)： EVAL-ADCMP566BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/16頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION ADCMP566BPZ
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，比較器
已用 IC / 零件： ADCMP566BPZ
已供物品： 板
相關(guān)產(chǎn)品： ADCMP566BCPZ-ND - IC COMP DUAL ULTRA-FAST 32LFCSP
ADCMP566
Rev. 0 | Page 8 of 16
TIMING INFORMATION
50%
VREF ± VOS
50%
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
LATCH ENABLE
tH
tPDL
tPDH
tPLOH
tPLOL
tR
tF
VIN
VOD
tS
tPL
03633-0-003
Figure 3. System Timing Diagram
The timing diagram in Figure 3 shows the ADCMP566 compare
and latch features. Table 4 describes the terms in the diagram.
Table 4. Timing Descriptions
Symbol
Timing
Description
tPDH
Input to output
high delay
Propagation delay measured from
the time the input signal crosses
the reference (± the input offset
voltage) to the 50% point of an
output low-to-high transition
tPDL
Input to output
low delay
Propagation delay measured from
the time the input signal crosses
the reference (± the input offset
voltage) to the 50% point of an
output high-to-low transition
tPLOH
Latch enable
to output high
delay
Propagation delay measured from
the 50% point of the Latch Enable
signal low-to-high transition to
the 50% point of an output low-
to-high transition
tPLOL
Latch enable
to output low
delay
Propagation delay measured from
the 50% point of the Latch Enable
signal low-to-high transition to
the 50% point of an output high-
to-low transition
Symbol
Timing
Description
tH
Minimum
hold time
Minimum time after the negative
transition of the Latch Enable
signal that the input signal must
remain unchanged to be acquired
and held at the outputs
tPL
Minimum
latch enable
pulsewidth
Minimum time that the Latch
Enable signal must be high to
acquire an input signal change
tS
Minimum
setup time
Minimum time before the
negative transition of the Latch
Enable signal that an input signal
change must be present to be
acquired and held at the outputs
tR
Output rise
time
Amount of time required to
transition from a low to a high
output as measured at the 20%
and 80% points
tF
Output fall
time
Amount of time required to
transition from a high to a low
output as measured at the 20%
and 80% points
VOD
Voltage
overdrive
Difference between the
differential input and reference
input voltages
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