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| 型號： | EVAL-ADCMP606BKSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADCMP606 |
| 標準包裝： | 1 |
| 系列： | * |
ADCMP606/ADCMP607
Rev. A | Page 12 of 16
The hysteresis control pin appears as a 1.25 V bias voltage seen
through a series resistance of 70 kΩ ± 20% throughout the
hysteresis control range. The advantages of applying hysteresis in
this manner are improved accuracy, improved stability, reduced
component count, and maximum versatility. An external bypass
capacitor is not recommended on the LE/HYS pin because it
impairs the latch function and often degrades the jitter perform-
ance of the device. As described in the Using/Disabling the
Latch Feature section, hysteresis control need not compromise
the latch function.
CROSSOVER BIAS POINTS
In both op amps and comparators, rail-to-rail inputs of this type
have a dual front-end design. Certain devices are active near the
VCCI rail and others are active near the VEE rail. At some predeter-
mined point in the common-mode range, a crossover occurs. At
this point, normally VCCI/2, the direction of the bias current
reverses and the measured offset voltages and currents change.
The ADCMP606/ADCMP607 comparators slightly elaborate
on this scheme. Crossover points are found at approximately
0.6 V and 1.6 V common mode.
MINIMUM INPUT SLEW RATE REQUIREMENT
With the rated load capacitance and normal good PCB design
practice, as discussed in the Optimizing Performance section,
these comparators should be stable at any input slew rate with
no hysteresis. Broadband noise from the input stage is observed
in place of the violent chattering seen with most other high
speed comparators. With additional capacitive loading or poor
bypassing, oscillation is observed. This oscillation is due to the
high gain bandwidth of the comparator in combination with
feedback parasitics in the package and PC board. In many
applications, chattering is not harmful.
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