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參數(shù)資料
| 型號(hào)： | EVAL-ADCMP607BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADCMP607 12LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 比較器，單路 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADCMP607 |
| 主要屬性： | CML 兼容輸出 |
| 次要屬性： | 鎖銷啟用和關(guān)機(jī)引腳 |
| 已供物品： | 板 |
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ADCMP606/ADCMP607
Rev. A | Page 5 of 16
TIMING INFORMATION
Figure 2 illustrates the ADCMP606/ADCMP607 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.
1.1V
50%
VN ± VOS
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
tH
tPDL
tPLOH
tF
VIN
VOD
tS
tPL
50%
Q OUTPUT
tPDH
tPLOL
tR
05
91
7-
0
25
Figure 2. System Timing Diagram
Table 2. Timing Descriptions
Symbol
Timing
Description
tF
Output fall time
Amount of time required to transition from a high to a low output as measured at the 20%
and 80% points.
tH
Minimum hold time
Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs.
tPDH
Input to output high delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.
tPDL
Input to output low delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.
tPL
Minimum latch enable pulse width
Minimum time that the latch enable signal must be high to acquire an input signal
change.
tPLOH
Latch enable to output high delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
tPLOL
Latch enable to output low delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
tR
Output rise time
Amount of time required to transition from a low to a high output as measured at the 20%
and 80% points.
tS
Minimum setup time
Minimum time before the negative transition of the latch enable signal occurs that an
input signal change must be present to be acquired and held at the outputs.
VOD
Voltage overdrive
Difference between the input voltages VA and VB.
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