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參數(shù)資料
| 型號： | EVAL-ADV7181CLQEBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/20頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADV7181CLQ |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 視頻，視頻解碼器 |
| 已用 IC / 零件： | ADV7181CLQ |
| 已供物品： | 板 |
ADV7181C
Data Sheet
Rev. E | Page 8 of 20
ANALOG SPECIFICATIONS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. TMIN to TMAX = 40°C to +85°C,
unless otherwise noted. Recommended analog input video signal range: 0.5 V to 1.6 V, typically 1 V p-p.
Table 4.
Parameter1, 2
Test Conditions
Min
Typ
Max
Unit
CLAMP CIRCUITRY
External Clamp Capacitor
0.1
F
Input Impedance; Except Pin 34 (FB)
Clamps switched off
10
M
Input Impedance of Pin 34 (FB)
20
k
CML
1.86
V
ADC Full-Scale Level
CML + 0.8
V
ADC Zero-Scale level
CML 0.8
V
ADC Dynamic Range
1.6
V
Clamp Level (When Locked)
CVBS input
CML – 0.292
V
SCART RGB input (R, G, B signals)
CML – 0.4
V
S-Video input (Y signal)
CML – 0.292
V
S-Video input (C signal)
CML – 0
V
Component input (Y, Pr, Pb signals)
CML – 0.3
V
PC RGB input (R, G, B signals)
CML – 0.3
V
Large Clamp Source Current
SDP only
0.75
mA
Large Clamp Sink Current
SDP only
0.9
mA
Fine Clamp Source Current
SDP only
17
A
Fine Clamp Sink Current
SDP only
17
A
1 The minimum/maximum specifications are guaranteed over this range.
2 Guaranteed by characterization.
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