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參數(shù)資料
| 型號(hào)： | EVAL-ADV7181DEBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 22/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR ADV7181D |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 視頻，視頻解碼器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADV7181D |
| 主要屬性： | NTSC/PAL/SECAM 數(shù)字視頻解碼器 |
| 次要屬性： | RGB 圖形數(shù)字化儀 |
| 已供物品： | 板 |
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Data Sheet
ADV7181D
Rev. A | Page 7 of 24
TIMING CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. TMIN to TMAX = 40°C to +85°C,
unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range.
Table 4.
Parameter1
Symbol
Description
Min
Typ
Max
Unit
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency
28.63636
MHz
Crystal Frequency Stability
±50
ppm
Horizontal Sync Input Frequency
14.8
110
kHz
LLC Frequency Range
12.825
75
MHz
SCLK Frequency
400
kHz
SCLK Minimum Pulse Width High
t1
0.6
μs
SCLK Minimum Pulse Width Low
t2
1.3
μs
Hold Time (Start Condition)
t3
0.6
μs
Setup Time (Start Condition)
t4
0.6
μs
SDATA Setup Time
t5
100
ns
SCLK and SDATA Rise Time
t6
300
ns
SCLK and SDATA Fall Time
t7
300
ns
Setup Time (Stop Condition)
t8
0.6
μs
RESET FEATURE
Reset Pulse Width
5
ms
CLOCK OUTPUTS
LLC Mark-Space Ratio
t9:t10
45:55
55:45
% duty
cycle
DATA AND CONTROL OUTPUTS
Data Output Transition Time
SDR (SDP)3
t11
Negative clock edge to start of valid data
3.6
ns
t12
End of valid data to negative clock edge
2.4
ns
SDR (CP)4
t13
End of valid data to negative clock edge
2.8
ns
t14
Negative clock edge to start of valid data
0.1
ns
DDR (CP)4, 5
t15
Positive clock edge to end of valid data
4 + TLLC/4
ns
t16
Positive clock edge to start of valid data
0.25 + TLLC/4
ns
t17
Negative clock edge to end of valid data
2.95 + TLLC/4
ns
t18
Negative clock edge to start of valid data
0.5 + TLLC/4
ns
1 Guaranteed by characterization.
2 TTL input values are 0 V to 3 V, with rise/fall times of ≤3 ns, measured between the 10% and 90% points.
3 SDP timing figures obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.
4 CP timing figures obtained using maximum drive strength value (0xFF) in Register Subaddress 0xF4.
5 DDR timing specifications dependent on LLC output pixel clock; TLLC/4 = 9.25 ns at LLC = 27 MHz.
Timing Diagrams
SDATA
SCLK
t5
t3
t4
t8
t6
t7
t2
t1
t3
09
99
4-
00
2
Figure 2. I2C Timing
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