參數(shù)資料
型號(hào): EVAL-ADV7611EB2Z
廠商: Analog Devices Inc
文件頁(yè)數(shù): 16/16頁(yè)
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR ADV7611
標(biāo)準(zhǔn)包裝: 1
系列: Advantiv®
主要目的: 視頻,HDMI 接收器
嵌入式: 是,MCU,ARM7
已用 IC / 零件: ADV7611
已供物品:
Data Sheet
ADV7611
Rev. D | Page 9 of 16
Pin No.
Mnemonic
Type
Description
25
LLC
Digital video output
Line-Locked Output Clock for the Pixel Data (Range is 13.5 MHz to 162.5 MHz).
26
P15
Digital video output
Video Pixel Output Port.
27
P14
Digital video output
Video Pixel Output Port.
28
P13
Digital video output
Video Pixel Output Port.
29
P12
Digital video output
Video Pixel Output Port.
30
P11
Digital video output
Video Pixel Output Port.
31
P10
Digital video output
Video Pixel Output Port.
32
P9
Digital video output
Video Pixel Output Port.
33
P8
Digital video output
Video Pixel Output Port.
34
DVDDIO
Power
Digital I/O Supply Voltage (3.3 V).
35
P7
Digital video output
Video Pixel Output Port.
36
P6
Digital video output
Video Pixel Output Port.
37
P5
Digital video output
Video Pixel Output Port.
38
P4
Digital video output
Video Pixel Output Port.
39
P3
Digital video output
Video Pixel Output Port.
40
DVDD
Power
Digital Core Supply Voltage (1.8 V).
41
P2
Digital video output
Video Pixel Output Port.
42
P1
Digital video output
Video Pixel Output Port.
43
P0
Digital video output
Video Pixel Output Port.
44
DVDDIO
Power
Digital I/O Supply Voltage (3.3 V).
45
DE
Miscellaneous digital
DE (data enable) is a signal that indicates active pixel data.
46
HS
Digital video output
HS is a horizontal synchronization output signal.
47
VS/FIELD/ALS
B
Digital input/output
VS is a vertical synchronization output signal. FIELD is a field synchronization output
signal in all interlaced video modes. VS or FIELD can be configured for this pin. The
ALSB allows selection of the I2C address.
48
AP
Miscellaneous digital
Audio Output Pin. Pin can be configured to output S/PDIF digital audio output
(S/PDIF) or I2S.
49
SCLK/INT2
Miscellaneous digital
A dual function pin that can be configured to output an audio serial clock or an
Interrupt 2 signal.
50
LRCLK
Miscellaneous digital
Audio Left/Right Clock.
51
MCLK/INT2
Miscellaneous digital
A dual function pin that can be configured to output an audio master clock or an
Interrupt 2 signal.
52
DVDD
Power
Digital Core Supply Voltage (1.8 V).
53
SCL
Miscellaneous digital
I2C Port Serial Clock Input. SCL is the clock line for the control port.
54
SDA
Miscellaneous digital
I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port.
55
INT1
Miscellaneous digital
Interrupt. This pin can be active low or active high. When status bits change, this pin is
triggered. The events that trigger an interrupt are under user configuration.
56
RESET
Miscellaneous digital
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required
to reset the ADV7611 circuitry.
57
PVDD
Power
PLL Supply Voltage (1.8 V).
58
XTALP
Miscellaneous analog
Input Pin for 28.63636 MHz Crystal or an External 1.8 V, 28.63636 MHz Clock Oscillator
Source to Clock the ADV7611.
59
XTALN
Miscellaneous analog
Crystal Input. Input pin for 28.63636 MHz crystal.
60
DVDD
Power
Digital Core Supply Voltage (1.8 V).
61
CEC
Digital input/output
Consumer Electronic Control Channel.
62
DDCA_SCL
HDMI input
HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant.
63
DDCA_SDA
HDMI input
HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input that is 5 V tolerant.
64
RXA_5V
HDMI input
5 V Detect Pin for Port A in the HDMI Interface.
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