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參數(shù)資料
| 型號(hào)： | EVAL-SSM2377Z |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR SSM2377 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類(lèi)型： | D 類(lèi) |
| 輸出類(lèi)型： | 1-通道（單聲道） |
| 在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量： | 3.17W x 1 @ 4 歐姆 |
| 電源電壓： | 2.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 板類(lèi)型： | 完全填充 |
| 已用 IC / 零件： | SSM2377 |
| 已供物品： | 板 |
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SSM2377
Rev. 0 | Page 14 of 16
When the user wants to send an input signal, an output pulse
(OUT+ and OUT) is generated to follow the input voltage. The
differential pulse density (VOUT) is increased by raising the input
signal level. Figure 36 depicts three-level, Σ-Δ output modulation
with and without input stimulus.
OUTPUT > 0V
+5V
0V
OUT+
+5V
0V
OUT–
+5V
0V
VOUT
OUTPUT < 0V
+5V
0V
OUT+
+5V
0V
OUT–
0V
–5V
VOUT
OUTPUT = 0V
OUT+
+5V
0V
+5V
0V
OUT–
+5V
–5V
0V
VOUT
0
98
24
-0
37
Figure 36. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus
LAYOUT
As output power increases, care must be taken to lay out PCB
traces and wires properly among the amplifier, load, and power
supply. A good practice is to use short, wide PCB tracks to decrease
voltage drops and minimize inductance. Ensure that track widths
are at least 200 mil for every inch of track length for lowest DCR,
and use 1 oz or 2 oz copper PCB traces to further reduce IR drops
and inductance. A poor layout increases voltage drops, conse-
quently affecting efficiency. Use large traces for the power supply
inputs and amplifier outputs to minimize losses due to parasitic
trace resistance.
Proper grounding guidelines help to improve audio performance,
minimize crosstalk between channels, and prevent switching
noise from coupling into the audio signal. To maintain high
output swing and high peak output power, the PCB traces that
connect the output pins to the load, as well as the PCB traces to
the supply pins, should be as wide as possible to maintain the
minimum trace resistances. It is also recommended that a large
ground plane be used for minimum impedances.
In addition, good PCB layout isolates critical analog paths from
sources of high interference. High frequency circuits (analog
and digital) should be separated from low frequency circuits.
Properly designed multilayer PCBs can reduce EMI emissions
and increase immunity to the RF field by a factor of 10 or more,
compared with double-sided boards. A multilayer board allows
a complete layer to be used for the ground plane, whereas the
ground plane side of a double-sided board is often disrupted by
signal crossover.
If the system has separate analog and digital ground and power
planes, the analog ground plane should be directly beneath the
analog power plane, and, similarly, the digital ground plane should
be directly beneath the digital power plane. There should be no
overlap between the analog and digital ground planes or between
the analog and digital power planes.
INPUT CAPACITOR SELECTION
The SSM2377 does not require input coupling capacitors if the
input signal is biased from 1.0 V to VDD 1.0 V. Input capacitors
are required if the input signal is not biased within this recom-
mended input dc common-mode voltage range, if high-pass
filtering is needed, or if a single-ended source is used. If high-
pass filtering is needed at the input, the input capacitor (CIN)
and the input impedance of the SSM2377 form a high-pass filter
with a corner frequency determined by the following equation:
fC = 1/(2π × 80 kΩ × CIN)
The input capacitor value and the dielectric material can
significantly affect the performance of the circuit. Not using
input capacitors can generate a large dc output offset voltage
and degrade the dc PSRR performance.
POWER SUPPLY DECOUPLING
To ensure high efficiency, low total harmonic distortion (THD),
and high PSRR, proper power supply decoupling is necessary.
Noise transients on the power supply lines are short-duration
voltage spikes. These spikes can contain frequency components
that extend into the hundreds of megahertz. The power supply
input must be decoupled with a good quality, low ESL, low ESR
capacitor, with a minimum value of 4.7 μF. This capacitor bypasses
low frequency noises to the ground plane. For high frequency
transient noises, use a 0.1 μF capacitor as close as possible to the
VDD pins of the device. Placing the decoupling capacitors as close
as possible to the SSM2377 helps to maintain efficient performance.
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