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參數(shù)資料
| 型號(hào)： | EVB90601 |
| 英文描述： | EVB90601 EValuation Board for the MLX90601 |
| 中文描述： | EVB90601評(píng)估板MLX90601 |
| 文件頁(yè)數(shù)： | 3/5頁(yè) |
| 文件大?。?/td> | 125K |
| 代理商： | EVB90601 |
MLX90255
Linear Optical Array
MLX90255 Linear Optical Array
Page 3 of 5
Rev 1.0 31-May-01
appropriate SI pulse to the optical array. The
required pull-down resistors are also foreseen
on the board. All important signals (SI, CLK,
VOUT, 5V and GND) are connected to test
terminals, which makes it easy to visualize them
on an oscilloscope. One sensor in a SMD
package is soldered on the PCB (called B) while
an external sensor can be connected to the 5-
pins connector row (upper right corner) (called
A). Both output signals are connected to test
terminals,
called
respectively
VOUTB
and
VOUTA.
An external regulated DC power supply, with an
output voltage between 6 and 10V, needs to be
connected to the screw connector in the upper
left corner of the PCB. A regular 9V battery is
also possible. (Mind the sign!) As soon as the
power supply is switched on, a LED lights up
and the micro controller starts generating the
CLK and SI signals with the selected frequency
and integration time.
The frequency of the signal CLK can be chosen
with the rotary DIL switch on the right. The
frequencies corresponding to the 16 positions of
this switch are shown in the following table.
Position
CLK frequency
0
36kHz
1
64kHz
2
77kHz
3
93kHz
4
112kHz
5
141kHz
6
170kHz
7
214kHz
8
284kHz
9
345kHz
A
435kHz
B
588kHz
C
909kHz
D
1.0MHz
E
1.25MHz
F
1.67MHz
Positions 0, E and F correspond to frequencies
that are outside the device specification. Lighting
up a second LED indicates selecting one of
them.
For
each
SI
pulse,
133
CLK
pulses
are
generated with the selected frequency, and after
them the CLK line is pulled low until the next SI
pulse. See further in this document for the
correct timings.
The light integration time can be selected with
the other rotary DIL switch. Again 16 positions
are possible, however now there is no one-to-
one relation with the corresponding integration
times. Actually the switch specifies a time which
starts only after the 133
rd CLK pulse. As the
integration time already starts after the 18
th pulse
(see device specification), the total integration
time also depends on the selected frequency.
The following table shows for each position (of
the ‘integration time switch’) the minimal and the
maximal
integration
time,
corresponding
to
respectively the maximal and the minimal CLK
frequency.
Total Integration Time
Position
Minimal
Maximal
0
79us
3.17ms
1
230us
3.33ms
2
380us
3.48ms
3
682us
3.77ms
4
985us
4.09ms
5
1.30ms
4.40ms
6
2.50ms
5.60ms
7
3.10ms
6.20ms
8
3.85ms
6.95ms
9
4.60ms
7.70ms
A
6.10ms
9.15ms
B
7.7ms
10.7s
C
9.15ms
12.5ms
D
10.5ms
E
15ms
F
20ms
The analog output voltage is directly proportional
to the light intensity and the integration time up
to the devices saturation level (3V typical). The
response of a pixel can be described with the
following formula:
VOUT = PR*Plight + offset + PRerror*Plight + DC
where DC means the dark current.
The
proportionality
constant
PR
is
the
responsivity
of
the
device
given
in
(V*cm2/W*sec).
Responsivity
is
wavelength
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