參數(shù)資料
型號(hào)： EVM142AHF
廠商： Semtech Corporation
英文描述： Per Pin timing Deskew w 4x2 Cross Point Switch
中文描述： 每個(gè)引腳的時(shí)間糾偏瓦特4x2交叉點(diǎn)開(kāi)關(guān)
文件頁(yè)數(shù)： 6/19頁(yè)
文件大?。?/td> 179K
代理商： EVM142AHF
6
2000 Semtech Corp.
www.semtech.com
EDGE HIGH-PERFORMANCE PRODUCTS
Circuit Description
(continued)
Edge142
Falling Edge Adjust
VFALL allows independent adjustment of the falling edge
(see Figure 3). The propagation delay for a falling edge
is defined as
Tpd- = Tpd(nom) + Tspan + Tfall
where Tfall is defined as the additional delay incurred by
adjusting the VFALL input. Notice that Tfall can be either
positive or negative over a
±
150 ps range, depending
on where VMID is set. This flexibility allows the part to
either expand or contract an input signal .
Notice also that Tpd+ is a function of VDELAY only, while
Tpd- is a function of VDELAY and VFALL. The transfer
function for Tspan vs. VDELAY is shown in Figure 4. The
transfer function for Tfall vs. VFALL is shown in Figure 5.
VMID
VMID is used in conjuction with VFALL to remove any
systematic pulse width expansion or contraction. VMID
and VFALL are differential analog voltage inputs which
affect the falling edge delay.
When VFALL equals VMID, there will be no programmed
pulse width variation between the input and the output
signal. It is the difference between VMID and VFALL
that expands or contracts a pulse.
VMID should be statically established at the midpoint of
the voltage swing of VFALL.
Programming Sequence
VDELAY, in addition to affecting the placement of the
rising edge, also affects the falling edge. Therefore, when
calibrating a system, VDELAY should be adjusted first.
As VFALL affects only the falling edge, it should be
adjusted after VDELAY is established.
Default Conditions
All digital inputs have either an internal pull up (to ground)
or pull down (to VEE) resistor (~50 K
) to protect against
floating inputs migrating to an indeterminant state. All
differential timing inputs are pulled to a logical zero state.
All operating mode control inputs are pulled down to a
logical zero. The mux select and mux enable inputs
have pull down resistors to VEE. And the output enable
is pulled up to ground.
The following chart summarizes the internal state of the
digital inputs.
However despite the internal resistors providing a known
default condition, it is recommended that no unused
inputs be left floating.
t
p
n
r
o
t
e
R
l
n
r
e
3
N
I
,
N
I
,
N
I
,
N
I
E
E
V
o
n
w
o
D
l
P
*
3
N
I
,
2
N
I
,
1
N
I
,
0
N
I
D
N
G
o
p
u
l
P
1
1
S
,
0
S
,
1
S
,
0
S
E
E
V
o
n
w
o
D
l
P
L
E
S
1
X
U
M
,
E
S
0
X
U
M
E
E
V
o
n
w
o
D
l
P
N
E
X
U
M
E
E
V
o
n
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o
D
l
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*
N
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p
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P
Figure 3. Falling Edge Control
INPUT
OUTPUT
(–1.3V < VDELAY < +0.1V)
VFALL = +0.1V
VFALL = –1.3V
TPDmin + Tspan + Tfall
TPDmin + Tspan
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