Revision 10 1-5 Other Architectural Features Performance The combination of architectural features described above enables eX devi" />
參數(shù)資料
型號(hào)： EX256-FTQ100
廠商： Microsemi SoC
文件頁(yè)數(shù)： 48/48頁(yè)
文件大?。?/td> 0K
描述： IC FPGA ANTIFUSE 12K 100-TQFP
標(biāo)準(zhǔn)包裝： 90
系列： EX
邏輯元件/單元數(shù)： 512
輸入/輸出數(shù)： 81
門(mén)數(shù)： 12000
電源電壓： 2.3 V ~ 2.7 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
eX Family FPGAs
Revision 10
1-5
Other Architectural Features
Performance
The combination of architectural features described above enables eX devices to operate with internal
clock frequencies exceeding 350 MHz for very fast execution of complex logic functions. The eX family is
an optimal platform upon which the functionality previously contained in CPLDs can be integrated. eX
devices meet the performance goals of gate arrays, and at the same time, present significant
improvements in cost and time to market. Using timing-driven place-and-route tools, designers can
achieve highly deterministic device performance.
User Security
Microsemi FuseLock advantage provides the highest level of protection in the FPGA industry against
unauthorized modifications. In addition to the inherent strengths of the architecture, special security
fuses that are intended to prevent internal probing and overwriting are hidden throughout the fabric of the
device. They are located such that they cannot be accessed or bypassed without destroying the rest of
the device, making Microsemi antifuse FPGAs highly resistant to both invasive and more subtle
noninvasive attacks.
Look for this symbol to ensure your valuable IP is secure. The FuseLock Symbol on the FPGA ensures
that the device is safeguarded to cryptographic attacks.
For more information, refer to Implementation of Security in Microsemi Antifuse FPGAs application note.
I/O Modules
Each I/O on an eX device can be configured as an input, an output, a tristate output, or a bidirectional
pin. Even without the inclusion of dedicated I/O registers, these I/Os, in combination with array registers,
can achieve clock-to-out (pad-to-pad) timing as fast as 3.9 ns. I/O cells in eX devices do not contain
embedded latches or flip-flops and can be inferred directly from HDL code. The device can easily
interface with any other device in the system, which in turn enables parallel design of system
components and reduces overall design time.
All unused I/Os are configured as tristate outputs by Microsemi's Designer software, for maximum
flexibility when designing new boards or migrating existing designs. Each I/O module has an available
pull-up or pull-down resistor of approximately 50 k
that can configure the I/O in a known state during
power-up. Just shortly before VCCA reaches 2.5 V, the resistors are disabled and the I/Os will be
controlled by user logic.
Figure 1-7 Fuselock
FuseLock
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EX256-FTQ100A 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:eX Family FPGAs
EX256-FTQ100I 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:eX Family FPGAs
EX256-FTQ100PP 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:eX Family FPGAs
EX256-FTQ128 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:eX Family FPGAs
EX256-FTQ128I 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:eX Family FPGAs
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