參數資料
| 型號： | EX256-FTQG100 |
| 廠商： | Microsemi SoC |
| 文件頁數： | 44/48頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA ANTIFUSE 12K 100-TQFP |
| 標準包裝： | 90 |
| 系列： | EX |
| 邏輯元件/單元數： | 512 |
| 輸入/輸出數： | 81 |
| 門數： | 12000 |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 100-LQFP |
| 供應商設備封裝： | 100-TQFP（14x14） |
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Revision 10
1-1
1 – eX FPGA Architecture and Characteristics
General Description
The eX family of FPGAs is a low-cost solution for low-power, high-performance designs. The inherent
low power attributes of the antifuse technology, coupled with an additional low static power mode, make
these devices ideal for power-sensitive applications. Fabricated with an advanced 0.22 mm CMOS
antifuse technology, these devices achieve high performance with no power penalty.
eX Family Architecture
Microsemi eX family is implemented on a high-voltage twin-well CMOS process using 0.22 m design
rules. The eX family architecture uses a “sea-of-modules” structure where the entire floor of the device is
covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing.
Interconnection among these logic modules is achieved using Microsemi patented metal-to-metal
programmable antifuse interconnect elements. The antifuse interconnect is made up of a combination of
amorphous silicon and dielectric material with barrier metals and has an "on" state resistance of 25
with
a capacitance of 1.0fF for low-signal impedance. The antifuses are normally open circuit and, when
programmed, form a permanent low-impedance connection. The eX family provides two types of logic
modules, the register cell (R-cell) and the combinatorial cell (C-cell).
The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable
(using the S0 and S1 lines) control signals (Figure 1-1). The R-cell registers feature programmable clock
polarity selectable on a register-by-register basis. This provides additional flexibility while allowing
mapping of synthesized functions into the eX FPGA. The clock source for the R-cell can be chosen from
either the hard-wired clock or the routed clock.
The C-cell implements a range of combinatorial functions up to five inputs (Figure 1-2 on page 1-2).
Inclusion of the DB input and its associated inverter function enables the implementation of more than
4,000 combinatorial functions in the eX architecture in a single module.
Two C-cells can be combined together to create a flip-flop to imitate an R-cell via the use of the CC
macro. This is particularly useful when implementing non-timing-critical paths and when the design
engineer is running out of R-cells. More information about the CC macro can be found in the Maximizing
Logic Utilization in eX, SX and SX-A FPGA Devices Using CC Macros application note.
Figure 1-1 R-Cell
DirectConnect
Input
CLKA,
CLKB,
Internal Logic
HCLK
CKS
CKP
CLR
PSET
Y
DQ
Routed
Data Input
S0
S1
相關PDF資料 |
PDF描述 |
|---|---|
| EX256-FTQ100 | IC FPGA ANTIFUSE 12K 100-TQFP |
| EP4CE10E22C8LN | IC CYCLONE IV FPGA 10K 144EQFP |
| BR93L86FJ-WE2 | IC EEPROM 16KBIT 2MHZ 8SOP |
| EP4CE10E22C7N | IC CYCLONE IV FPGA 10K 144EQFP |
| AGL250V5-CS196I | IC FPGA 1KB FLASH 250K 196-CSP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| EX256-FTQG100A | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:eX Family FPGAs |
| EX256-FTQG100I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:eX Automotive Family FPGAs |
| EX256-FTQG100PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:eX Family FPGAs |
| EX256-PCS100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:eX Family FPGAs |
| EX256-PCS100A | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:eX Family FPGAs |
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