3-2 Revision 10 v4.0 (continued) The "Flexible Mode" section was updated. 1-10 Table 1-5 Boundary-Scan Pin Configu" />
參數(shù)資料
型號(hào): EX64-TQG64
廠商: Microsemi SoC
文件頁(yè)數(shù): 39/48頁(yè)
文件大?。?/td> 0K
描述: IC FPGA ANTIFUSE 3K 64-TQFP
標(biāo)準(zhǔn)包裝: 160
系列: EX
邏輯元件/單元數(shù): 128
輸入/輸出數(shù): 41
門(mén)數(shù): 3000
電源電壓: 2.3 V ~ 2.7 V
安裝類(lèi)型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
Datasheet Information
3-2
Revision 10
v4.0
(continued)
The "Flexible Mode" section was updated.
The "TRST Pin" section was updated.
The "Programming" section was updated.
All VSV pins were changed to VCCA. The change affected the following pins:
64-Pin TQFP –
Pin 36
100-Pin TQFP –
Pin 57
49-Pin CSP –
Pin D5
128-Pin CSP–
Pin H11 and Pin J1 for eX256
180-Pin CSP –
Pins J12 and K2
v3.0
The "eX Timing Model" section has been updated.
v2.0.1
The I/O Features table, Table 1-2 on page 1-6, was updated.
The table in the section, "Package Thermal Characteristics" section has been updated
for the 49-Pin CSP.
The "eX Timing Model" section has been updated.
The timing numbers found in, "eX Family Timing Characteristics" section have been
updated.
The VSV pin has been added to the "Pin Description" section.
Please see the following pin tables for the VSV pin and an important footnote including
the pin: "TQ64", "TQ100", "128-Pin CSP", and "180-Pin CSP".
2-6, 2-11
The figure, "TQ64" section has been updated.
Revision
Changes
Page
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