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參數(shù)資料
| 型號： | FAN1851A |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Ground Fault Interrupter |
| 中文描述： | 接地故障遮斷 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 122K |
| 代理商： | FAN1851A |
FAN1851A
PRODUCT SPECIFICATION
6
REV. 2.0.1 6/17/05
Application Information
A typical ground fault interrupter circuit is shown in
Figure 10. It is designed to operate on 120 VAC line voltage
with 5mA normal fault sensitivity.
A full-wave rectifier bridge and a 15k
Ω
/2W resistor are used
to supply the DC power required by the IC. A 1 μF capacitor
at the "+V
S
" pin is used to filter the ripple of the supply volt-
age and is also connected across the SCR to allow firing of
the SCR on either half-cycle. When a fault causes the SCR to
trigger, the circuit breaker is energized and line voltage is
removed from the load.
At this time no fault current flows and the C
T
discharge cur-
rent increases from I
TH
to 3I
TH
(see Block Diagram). This
quickly resets both the timing capacitor and the output latch.
The circuit breaker can be reset and the line voltage again
supplied to the load, assuming the fault has been removed.
A 1000:1 sense transformer is used to detect the normal
fault. The fault current, which is basically the difference in
current between the hot and neutral lines, is stepped down by
1000 and fed into the input pin of the operational amplifier
through a 10μF capacitor. The 0.0033μF capacitor between
the "- Input" pin and the "+ Input" pin and the 200pF capaci-
tor between "+ Input" and "Ground" pins are added to obtain
better noise immunity. The normal fault sensitivity is deter-
mined by the timing capacitor discharging current, I
TH
. I
TH
can be calculated by:
(1)
At the decision point, the average fault current just equals
the threshold current, I
TH
.
(2)
Where I
F
(rms) is the rms input fault current to the opera-
tional amplifier and the factor of 2 is due to the fact that I
F
charges the timing capacitor only during one half-cycle,
while I
TH
discharges the capacitor continuously. The factor
0.91 converts the rms value to an average value. Combining
equations (1) and (2) we have:
(3)
For example, to obtain 5mA(rms) sensitivity for the circuit
in Figure 7 we have:
(4)
I
TH
R
SET
---7V
2
÷
=
I
TH
I
rms
2
)
-------------------
0.91
×
=
R
SET
)
I
F
rms
(
0.91
×
-------------7V
=
R
SET
1000
5 mA
0.91
----------7V
1.5M
Ω
=
=
The correct value for R
SET
can also be determined from the
characteristic curve that plots equation (3). Note that this is
an approximate calculation; the exact value of R
SET
depends
on the specific sense transformer used and FAN1851A toler-
ances. Inasmuch as UL943 specifies a sensitivity “window”
of 4mA to 6mA, a provision should be made to adjust R
SET
with a potentiometer.
Independent of setting sensitivity, the desired integration
time can be obtained through proper selection of the timing
capacitor, C
T
. Due to the large number of variables involved,
proper selection of C
T
is best done empirically. The follow-
ing design example should only be used as a guideline.
Assume the goal is to meet UL943 timing requirements.
Also assume that worst case timing occurs during GFI
start-up (S1 closure) with both a heavy normal fault and a
2
Ω
grounded neutral fault present. This situation is shown in
Figure 8.
Figure 8. Example
UL943 specifies
≤
25ms average trip time under these condi-
tions. Calculation of C
T
based upon charging currents due to
normal fault only is as follows:
1.
Start with a
≤
25ms specification. Subtract 3ms GFI
turn-on time (15k
Ω
and 1μF). Subtract 8ms potential
loss of one half-cycle due to fault current sense of
half-cycles only.
2.
Subtract 4ms time required to open a sluggish circuit
breaker.
3.
This gives a total
≤
10ms maximum integration time
that could be allowed.
4.
To generate 8ms value of integration time that accom-
modates component tolerances and other variables:
(5)
Line
Neutral
Hot
S1
GFI
Hot
Neutral
R
B
500
I
R
B
500
(0.2)I
(0.8)I
R
N
0.4
C
T
I
T
×
V
=
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