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參數(shù)資料
| 型號： | FAN3506 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | PC SMPS Secondary Side Control IC |
| 中文描述： | 5-CHANNEL POWER SUPPLY SUPPORT CKT, PDIP16 |
| 封裝： | 0.300 INCH, DIP-16 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 191K |
| 代理商： | FAN3506 |
FAN3506
7
3. Latch & FPO Output
Power Good Signal Generator circuits generate "On & Off" signal depending on the status of output voltage to prevent the
malfunctions of following systems like microprocessor and etc. from unstable outputs at power on & off .
At Power On, it produces PG "High" signal after some delay (300ms_Typ) for stabilizing outputs.
At power Off, it produces PG "Low" signal without delay by sensing the status of power source for protecting following
systems. COMP6 creates PG "Low" without delay when +5V output falls to less than 4.3V to prevent some malfunction at
transient status, thus it improves system stability. FAN3506 detects the Under Voltage level of three
outputs(+3.3V/+5V/+12V) and PGI, respectively.
- UV Deducing Level of +3.3V : Vuv33 = 2.8V(Typ)
- UV Deducing Level of +5V : Vuv5 = 4.3V(Typ)
- UV Deducing Level of +12V : Vuv12 = 10.3V(Typ)
- UV Deducing Level of PGI
: Vpgi = 1.26V(Typ)
When PSON signal is high, it generates PG "Low" signal without delay. It means that PG becomes "Low" before main power
is grounded. PG delay time(Td(PG)) is determined by capacitor value, threshold voltage of COMP6 and the charging current
and its equation is as following.
Td(PG) = (Ctpg * VthH) / Ichg = 300ms(Typ)
OVP
L
L
H
H
SET
L
L
H
H
RESET
L
H
L
H
Qn+1
Qn
L
H
L
Qn+1
Qn
H
L
H
PC800-1
R8
1K
FPO
6
Q1
Q100
PC800-2
OVP
PSON
7
PWM IC
(KA38XX)
1
2
+5Vsb
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