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參數(shù)資料
| 型號： | FAN3850AUC16X |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MICROPHONE PRE-AMP 6-WLCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | AB 類 |
| 輸出類型： | 1-通道（單聲道） |
| 電源電壓： | 1.64 V ~ 3.63 V |
| 特點： | ADC，麥克風(fēng) |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 6-WLCSP |
| 封裝/外殼： | 6-XFBGA，WLCSP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | FAN3850AUC16XFSDKR |
2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN3850A Rev. 3.0.6
5
FAN3850A
—
Microphone
Pre-Amp
lifier
with
Digita
lOutput
Electrical Characteristics (Continued)
Unless otherwise specified, all limits are guaranteed for TA=25°C, VDD=1.8V, VIN=94dB(SPL), and fCLK=2.4MHz.
Duty Cycle=50% and CMIC=15pF.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
tA
Time from CLOCK Transition
to Data becoming Valid
On Falling Edge of CLOCK,
SELECT=GND, CLOAD=15pF
18
43
ns
tB
Time from CLOCK Transition
to Data becoming HIGH-Z
On Rising Edge of CLOCK,
SELECT=GND, CLOAD=15pF
0
5
16
ns
tA
Time from CLOCK Transition
to Data becoming Valid
On Rising Edge of CLOCK,
SELECT=VDD, CLOAD=15pF
18
56
ns
tB
Time from CLOCK Transition
to Data becoming HIGH-Z
On Falling Edge of CLOCK,
SELECT=VDD, CLOAD=15pF
0
5
16
ns
fCLK
Input CLOCK Frequency
(8)
Active Mode
1.0
2.4
4.0
MHz
CLKdc
CLOCK Duty Cycle
(4)
40
50
60
%
tWAKEUP
Wake-Up Time
(9)
fCLK=2.4MHz
0.35
2.00
ms
tFALLASLEEP
Fall-Asleep Time
(10)
fCLK=2.4MHz
0
0.01
1.00
ms
CLOAD
Load Capacitance on Data
100
pF
Notes:
3.
Pseudo-random noise with triangular probability density function. Bandwidth up to 10MHz.
4.
Guaranteed by characterization.
5.
Assuming that 120dB(SPL) is mapped to 0dBFS.
6.
Assuming an input of -45dBV
7.
Guaranteed by design.
8.
All parameters are tested at 2.4MHz. Frequency range guaranteed by characterization.
9.
Device wakes up when fCLK 300kHz.
10. Device falls asleep when fCLK 70kHz.
Figure 3. Interface Timing
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