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參數(shù)資料
| 型號： | FAN5056V90M |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 266K |
| 代理商： | FAN5056V90M |
FAN5056V85/FAN5056V90
2
REV. 0.8.0 1/31/01
Pr
eliminar
y
Specication
external divider. The FAN5056 also offers integrated functions
including open-collector Power Good, Output Enable/Soft
Start and current limiting, and is available in a 24 pin SOIC
package.
Pin Assignments
24
23
22
21
20
19
18
17
16
15
14
13
FAN5056
HIDRV
SW
GNDA
VID4/VID25mV
VID3
VID2
VID1
VID0
VTTGATE
VTTFB
VCKGATE
VCKFB
VCCP
LODRV
GNDP
VCCA
VFB
DROOP
ILIM
PWRGD
SS/ENABLE
TYPEDET
VAGPGATE
VAGPFB
1
2
3
4
5
6
7
8
9
10
11
12
Pin Denitions
Pin Number
Pin Name
Pin Function Description
1
HIDRV
High Side FET Driver. Connect this pin to the gate of an N-channel MOSFET. The
trace from this pin to the MOSFET gate should be <0.5".
2SW
High Side Driver Source and Low Side Driver Drain Switching Node. Together
with DROOP and ILIM pins allows FET sensing for VCC current.
3
GNDA
Analog Ground. Return path for low power analog circuitry. This pin should be
connected to a low impedance system ground plane to minimize ground loops.
4
VID4/
VID25mV
Multi-Value Voltage Identification Code Input. This open collector/TTL
compatible input will program the output voltage over the ranges specified in Table
1 (for the FAN5056V90) or Table 2 (for the FAN5056V85). A pull-up resistor is
internal to the controller.
5-8
VID3-0
Voltage Identification Code Inputs. These open collector/TTL compatible inputs
will program the output voltage over the ranges specified in Table 1 (for the
FAN5056V90) or Table 2 (for the FAN5056V85). Pull-up resistors are internal to the
controller.
9
VTTGATE
Gate Driver for VTT Transistor. For 1.5V output.
10
VTTFB
Voltage Feedback for VTT.
11
VCKGATE
Gate Driver for VCK Transistor. For 2.5V output.
12
VCKFB
Voltage Feedback for VCK.
13
VAGPFB
Voltage Feedback for VAGP.
14
VAGPGATE
Gate Driver for VAGP Transistor. For 3.3/1.5V output.
15
TYPEDET
Type Detect. Sets 3.3V or 1.5V for AGP.
16
ENABLE/SS
Output Enable. A logic LOW on this pin will disable all outputs. An internal current
source allows for open collector control. This pin also doubles as soft start for all
outputs.
17
PWRGD
Power Good Flag. An open collector output that will be logic LOW if any output
voltage is not within ±14% of the nominal output voltage setpoint.
18
ILIM
VCC Current Feedback. Pin 18 is used in conjunction with pin 2 as the input for the
VCC current feedback control loop. Layout of these traces is critical to system
performance. See Application Information for details.
19
DROOP
Droop Set. Use this pin to set magnitude of active droop.
20
VFB
Vcc Voltage Feedback. Pin 20 is used as the input for the VCC voltage feedback
control loop. See Application Information for details regarding correct layout.
21
VCCA
Analog VCC. Connect to system 5V supply and decouple with a 0.1F ceramic
capacitor.
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