
PRODUCT SPECIFICATION
FAN5059
REV. 1.0.4 8/14/03
13
The softstart ramp begins at T(0) where UVLO is released.
During the period of t
1
the softstart pin ramps but the PWM
switching is not enabled and thus the duty cycle is zero
(D=0) and the output voltage is zero. During t
2
the duty
cycle increased progressively from 0 to 1. This period is
where the output voltage ramps, dependent on output capaci-
tance and output load. If the duration of t
2
is long enough
the output voltage will fully ramp to the point of regulation.
During t
3
the softstart pin continues to ramp but without
effect on the output voltage.
NOTE: If a very large output capacitor bank is used it may
be required to use a larger C
SS
to ensure a full output voltage
ramp within t
2
.
Over-Voltage Protection
The FAN5059 constantly monitors the output voltage for pro-
tection against over-voltage conditions. If the voltage at the
VFB pin exceeds the selected program voltage, an over-volt-
age condition is assumed and the FAN5059 disables the out-
put drive signal to the external high-side MOSFET. The DC-
DC converter returns to normal operation after the output
voltage returns to normal levels.
Oscillator
The FAN5059 oscillator section uses a fixed frequency of
operation of 300KHz.
Design Considerations and Component
Selection
Additional information on design and component selection
may be found in Fairchild’s Application Note 57.
MOSFET Selection
This application requires N-channel Logic Level Enhancement
Mode Field Effect Transistors. Desired characteristics are as
follows:
Low Static Drain-Source On-Resistance, R
DS,ON
< 20m
(lower is better)
Low gate drive voltage, V
GS
= 4.5V rated
Power package with low Thermal Resistance
Drain-Source voltage rating > 15V.
The on-resistance (R
DS,ON)
is the primary parameter for
MOSFET selection. The on-resistance determines the power
dissipation within the MOSFET and therefore significantly
affects the efficiency of the DC-DC Converter. For details
and a spreadsheet on MOSFET selection, refer to Applica-
tions Bulletin AB-8.
Inductor Selection
Choosing the value of the inductor is a tradeoff between
allowable ripple voltage and required transient response. The
system designer can choose any value within the allowed
minimum to maximum range in order to either minimize ripple
or maximize transient performance. The first order equation
(close approximation) for minimum inductance is:
where:
V
in
= Input Power Supply
V
out
= Output Voltage
f = DC/DC converter switching frequency
ESR = Equivalent series resistance of all output capacitors in
parallel
V
ripple
= Maximum peak to peak output ripple voltage budget.
The first order equation for maximum allowed inductance is:
where:
C
o
= The total output capacitance
I
pp
= Maximum to minimum load transient current
V
tb
= The output voltage tolerance budget allocated to load
transient
D
m
= Maximum duty cycle for the DC/DC converter (usually
95%).
Some margin should be maintained away from both L
min
and
L
max
. Adding margin by increasing L almost always adds
expense since all the variables are predetermined by system
performance except for C
O
, which must be increased to
increase L. Adding margin by decreasing L can be done by
purchasing capacitors with lower ESR. The FAN5059
provides significant cost savings for the newer CPU systems
that typically run at high supply current.
FAN5059 Short Circuit Current Characteristics
The FAN5059 protects against output short circuit on the
core supply by turning off both the high-side and low-side
MOSFETs and resetting softstart. The short circuit limit is
set with the R
S
resistor, as given by the formula
Note: R
S
cannot exceed 10.8K. If a higher current is required
than 10.8K allows, a FET with lower R
DSon
must be used.
5V
2.75V
2.25V
t
1
t
2
t
3
V
SS
T
T(0)
L
min
(Vin – V
out
)
f
x
V
out
V
in
x
ESR
V
ripple
=
L
max
(Vin – V
out
) D
m
V
tb
I
pp2
=
2C
O
R
S
I
SC
*R
DS, on
I
Detect
=