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參數(shù)資料
| 型號(hào)： | FAN5063M |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Power Supply Switching Circuit |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁(yè)數(shù)： | 4/14頁(yè) |
| 文件大小： | 196K |
| 代理商： | FAN5063M |
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FAN5063
PRODUCT SPECIFICATION
4
REV. 1.0.0 12/4/00
Note:
1. Voltage Regulation includes Initial Voltage Setpoint and Output Temperature Drift.
Electrical Speci
fi
cations
(V
+5VSTBY
= V
+5VMAIN
The denotes specifications which apply over the full operating temperature range.
=5V, V
+3.3V
= 3.3V, V+12V = 12V and T
A
= +25°C using circuit in Figure 4, unless otherwise noted.)
Parameter
+3.3V DUAL
V
Out1
, On
V
Out1
, Off
V
Out2
, On
Total Output Voltage Variation
Maximum Drive Current
Minimum Load Current
Overcurrent Limit: Undervoltage
Overcurrent Delay Time
Output Driver Deadtime
Conditions
Min.
Typ.
Max.
Units
10
V
I = 10μA
Standby
3VOUT2 On
3VOUT1 On
3VOUT2 On
200
mV
mA
V
mA
mA
%Vout
μsec
μsec
nsec
5
1
3.135
100
3.3
3.465
50
80
150
See Figure 2: Main
→
Standby
→
Main
2
6
: Standby
200
1000
VADJ DUAL
I
B
V
V
R
O
> 3.3V
≤
3.3V
= R
100
150
2.375
1.25
mA
mA
V
V
%Vref
μsec
μsec
O
Total Voltage Variation
Vadj Output Voltage Range
Overcurrent Limit
Overcurrent Delay Time
Output Driver Overlap Time
Common Functions
Charge Pump Frequency
+5VSTBY UVLO
+5VSTBY UVLO Hysteresis
+12V UVLO
+12V UVLO Hysteresis
+5VSTBY Current
+12V Current
Input Logic HIGH
Input Logic LOW
Softstart Current
Control Line Input Current
Over Temperature Shutdown
1
1
2
= 10K
2.5
2.625
3.5
80
150
See Figure 2
1
5
250
4.5
0.5
7.5
800
10
2.5
KHz
V
V
V
mV
mA
mA
V
V
μA
μA
°C
MAIN Power Present
25
10
2.0
0.8
6
SLP_S5, SLP_S3, PWROK
100
150
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