FAN5066
PRODUCT SPECIFICATION
2
REV. 2.1.4 11/13/01
Pin Assignments
Pin Definitions
Pin Number Pin Name
1
Pin Function Description
Oscillator Capacitor Connection
the internal oscillator frequency. Layout of this pin is critical to system performance.
See Application Information for details.
Output Enable
. A logic LOW on this pin will disable the output. An internal pull-up
resistor allows for either open collector or TTL compatibility.
Power Good Flag
. An open collector output that will be at logic LOW if the output
voltage is not within
±
12% of the nominal output voltage setpoint.
High Side Current Feedback
. Pins 4 and 5 are used as the inputs for the current
feedback control loop. Layout of these traces is critical to system performance. See
Application Information for details.
Voltage Feedback
. Pin 5 is used as the input for the voltage feedback control loop and
as the low side current feedback input. See Application Information for details regarding
correct layout.
Analog VCC
. Connect to system 5V supply and decouple with a 0.1
capacitor.
Power VCC for low side FET driver
. Connect to system 5V supply and place a 1
ceramic capacitor for decoupling and local charge storage.
VID4 Input
. A logic 1 on this open collector/TTL input will enable the VID3–VID0 inputs
to set the output from 2.1V to 3.5V, and a logic 0 will set the output from 1.3V to 2.05V,
as shown in Table 1. Pullup resistors are internal to the controller.
Low Side FET Driver
. Connect this pin to the gate of an N-channel MOSFET for
synchronous operation. The trace from this pin to the MOSFET gate should be < 0.5".
Power Ground
. Return pin for high currents flowing in pins 7 and 13 (VCCP and
VCCQP). Connect to a low impedance ground.
High Side FET Driver
. Connect this pin to the gate of an N-channel MOSFET. The
trace from this pin to the MOSFET gate should be < 0.5".
Power VCC
. For high side FET driver. VCCQP must be connected to a voltage of at
least VCCA + V
GS,ON
(MOSFET), and place a 1
and local charge storage. See Application Information for details
Digital Ground
. Return path for digital logic. Connect to a low impedance system
ground plane to minimize ground loops.
Analog Ground
. Return path for low power analog circuitry. This pin should be
connected to a low impedance system ground plane to minimize ground loops.
Voltage Control
. The voltage forced on this pin determines the output voltage of the
converter.
Voltage Identification Code Inputs
. These open collector/TTL compatible inputs will
program the output voltage of the reference over the ranges specified in Table 1.
Pull-up resistors are internal to the controller.
Reference Voltage Test Point
. This pin provides access to the DAC output and should
be decoupled to ground using 0.1μF capacitor.
CEXT
. Connecting an external capacitor to this pin sets
2
ENABLE
3
PWRGD
4
IFB
5
VFB
6
VCCA
μ
F ceramic
7
VCCP
μ
F
8
VID4
9
LODRV
10, 11
GNDP
12
HIDRV
13
VCCQP
μ
F ceramic capacitor for decoupling
14
GNDD
15
GNDA
16
CNTRL
17-19
VID1-VID3
20
VREF
1
2
3
4
5
6
8
7
VREF
VID1
VID2
VID3
CNTRL
GNDA
GNDD
VCCQP
20
19
18
17
16
15
13
9
12
10
11
14
CEXT
ENABLE
PWRGD
IFB
VFB
VCCA
VCCP
FAN5066
VID4
GNDP
HIDRV
GNDP
LODRV