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參數(shù)資料
| 型號： | FAN5069EMTCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | PWM and LDO Controller Combo |
| 中文描述： | 0.15 A SWITCHING CONTROLLER, 600 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | LEAD FREE, TSSOP-16 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大小： | 379K |
| 代理商： | FAN5069EMTCX |
3
www.fairchildsemi.com
FAN5069 Rev. 1.1.0
F
Pin Assignment
Figure 2. Pin Assignment
Pin Description
Pin No.
Pin Name
Pin Description
1
FBLDO
LDO Feedback
. This node is regulated to V
REF
.
Oscillator Set Resistor.
This pin provides oscillator switching frequency adjustment. By placing
a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased.
2
R(T)
3
ILIM
Current Limit.
A resistor from this pin to GND sets the current limit.
4
SS
Soft-Start.
A capacitor from this pin to GND programs the slew rate of the converter and the LDO
during initialization. It also sets the time by which the converter will delay when restarting after a
fault occurs. SS has to reach 1.2V before fault shut-down feature is enabled. The LDO is enabled
when SS reaches 2.2V.
5
COMP
COMP.
The output of the error amplifier drives this pin.
6
FB
Feedback.
This pin is the inverting input of the internal error amplifier. Use this pin, in combina-
tion with the COMP pin, to compensate the feedback loop of the converter.
7
EN
Enable.
Enables operation when pulled to logic high. Toggling EN will also reset the regulator
after a latched fault condition. This is a CMOS input whose state is indeterminate if left open and
hence needs to be properly biased at all times.
8
AGND
Analog Ground.
The signal ground for the IC. All internal control voltages are referred to this pin.
Tie this pin to the ground island/plane through the lowest impedance connection available.
9
SW
Switching Node.
Return for the high-side MOSFET driver and a current sense input. Connect to
source of high-side MOSFET and drain of low-side MOSFET.
10
HDRV
High-Side Gate Drive Output.
Connect to the gate of the high-side power MOSFETs. This pin is
also monitored by the adaptive shoot-through protection circuitry to determine when the high-side
MOSFET is turned off.
11
BOOT
Bootstrap Supply Input.
Provides a boosted voltage to the high-side MOSFET driver. Connect
to bootstrap capacitor as shown in Figure 1.
12
PGND
Power Ground.
The return for the low-side MOSFET driver. Connect to source of low-side MOS-
FET.
13
LDRV
Low-Side Gate Drive Output.
Connect to the gate of the low-side power MOSFETs. This pin is
also monitored by the adaptive shoot-through protection circuitry to determine when the lower
MOSFET is turned off.
14
R(RAMP)
Ramp Resistor
. A resistor from this pin to VIN sets the ramp amplitude and provides voltage
feed-forward.
15
VCC
VCC.
Provides bias power to the IC and the drive voltage for LDRV. Bypass with a ceramic
capacitor as close to this pin as possible. This pin has a shunt regulator which will draw current
when the input voltage is above 5.6V.
16
GLDO
Gate Drive for the LDO.
Turned off (low) until SS is greater than 2.2V.
16-Lead TSSOP
Top View
FAN5069
16
15
14
13
12
11
10
9
GLDO
VCC
R(RAMP)
LDRV
PGND
BOOT
HDRV
SW
FBLDO
R(T)
ILIM
SS
COMP
FB
EN
AGND
1
2
3
4
5
6
7
8
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