參數(shù)資料
型號： FAN5069MTCX
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 穩(wěn)壓器
英文描述： PWM and LDO Controller Combo
中文描述： 0.15 A SWITCHING CONTROLLER, 600 kHz SWITCHING FREQ-MAX, PDSO16
封裝： LEAD FREE, TSSOP-16
文件頁數(shù)： 16/20頁
文件大小： 379K
代理商： FAN5069MTCX
16
www.fairchildsemi.com
FAN5069 Rev. 1.1.0
F
Poles and Zeros of Plant Transfer Function:
Plant zero frequency =
(EQ. 26)
Plant 1
st
pole frequency =
(EQ. 27)
Plant 2
nd
pole frequency =
(EQ. 28)
Plant 3
rd
pole frequency =
(EQ. 29)
Plant gain (magnitude) response:
(EQ. 30)
Plant phase response:
(EQ. 31)
Choose R1, R
BIAS
to set the output voltage using EQ.5. Choose
the zero cross over frequency F
cross
of the overall loop. Typically
F
cross
should be less than 1/5th of F
sw
. Choose the desired
phase margin. Typically this number should be between 60° to
90°.
Calculate plant gain at F
cross
using EQ.28 by substituting F
cross
in place of f. The gain that the amplifier needs to provide to get
the required cross over is given by
(EQ. 32)
The phase boost required is calculated as given in (EQ. 33).
(EQ. 33)
Where, M is the desired phase margin in degrees and P is the
modulator phase shift in degrees at the time of crossover.
The feedback component values are now calculated as given in
equations below:
(EQ. 34)
(EQ. 35)
(EQ. 36)
(EQ. 37)
(EQ. 38)
(EQ. 39)
Layout Considerations
The switching power converter layout needs careful attention
and is critical to achieving low losses and clean and stable oper-
ation. Below are specific recommendations for a good board
layout:
■
Keep the high current traces and load connections as short
as possible.
■
Use thick copper boards whenever possible to achieve higher
efficiency.
■
Keep the loop area between the SW node, low-side MOS-
FET, inductor and the output capacitor as small as possible.
■
Route high dV/dt signals such as SW node away from the
error amplifier input/output pins. Keep components con-
nected to these pins close to the pins.
■
Place ceramic de-coupling capacitors very close to VCC pin.
■
All input signals are referenced with respect to AGND pin.
Dedicate one layer of the PCB for a GND plane. Use at least
4 layers for the PCB.
■
Minimize GND loops in the layout to avoid EMI related
issues.
■
Use wide traces for the lower gate drive to keep the drive
impedances low.
■
Connect PGND directly to the lower MOSFET source pin.
■
Use wide land areas with appropriate thermal vias to effec-
tively remove heat from the MOSFET’s.
■
Use snubber circuits to minimize high frequency ringing at
the SW nodes.
■
Place the output capacitor for the LDO close to the source of
the LDO MOSFET.
f
z
o
es
-----------------------------------------
=
f
p1
2
π
C
o
R
p
e
R
L
------
+
×
×
×
---------------------------------------------------------
=
f
p2
π
------------
o
L
-------------------
p
L
e
------
+
×
=
f
p3
2
e
R
p
×
×
π
-------------------------
=
G
p
(f)
20
M
0
log
10
1
f
f
p2
---
2
+
1
f
p1
------
+
1
------
+
1
f
p3
------
2
+
×
×
-------------------------------------------------------------------------------------------------------
log
×
+
×
=
G
P
(f)
∠
tan
1
–
f
z
---
tan
1
–
f
f
p1
------
–
tan
1
–
f
f
p2
------
–
tan
1
–
f
f
p3
------
–
–
=
G
AMP
p
cross
)
---------------------------------
=
Phase Boost
M
P
–
90
°
–
=
K
Tan
----------------
45
+
2
=
C1
cross
K
–
AMP
--------------------------------------------------------------------------
=
C2
C1
1
(
)
×
=
C3
2
π
F
cross
K
×
×
×
R3
×
-----------------------------------------------------------------
=
R2
cross
--------------------------------------------------
=
R3
1
–
)
-----------------
=
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