參數(shù)資料
型號(hào): FAN5236QSC
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: Dual Mobile-Friendly DDR / Dual-output PWM Controller
中文描述: DUAL SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO28
封裝: QSOP-28
文件頁數(shù): 15/20頁
文件大小: 199K
代理商: FAN5236QSC
FAN5236
PRODUCT SPECIFICATION
REV. 1.1.7 4/4/03
15
Output Capacitor Selection
The output capacitor serves two major functions in a switch-
ing power supply. Along with the inductor it filters the
sequence of pulses produced by the switcher, and it supplies
the load transient currents. The output capacitor require-
ments are usually dictated by ESR, Inductor ripple current
(
I) and the allowable ripple voltage (
V).
In addition, the capacitor’s ESR must be low enough to allow
the converter to stay in regulation during a load step. The
ripple voltage due to ESR for the converter in Figure 5 is
120mV P-P. Some additional ripple will appear due to the
capacitance value itself:
which is only about 1.5mV for the converter in Figure 5 and
can be ignored.
The capacitor must also be rated to withstand the RMS
current which is approximately 0.3 X (
I), or about 400mA
for the converter in Figure 5. High frequency decoupling
capacitors should be placed as close to the loads as
physically possible.
Input Capacitor Selection
The input capacitor should be selected by its ripple current
rating.
Two-Stage Converter Case
In DDR mode (Figure 4), the VTT power input is powered
by the VDDQ output, therefore all of the input capacitor rip-
ple current is produced by the VDDQ converter. A conserva-
tive estimate of the output
current required for the 2.5V regulator is:
As an example, if average I
VDDQ
is 3A, and average I
VTT
is
1A, I
VDDQ
current will be about 3.5A. If average input volt-
age is 16V, RMS input ripple current will be:
where D is the duty cycle of the PWM1 converter:
therefore:
Dual Converter 180° phased
In Dual mode (Figure 5), both converters contribute to the
capacitor input ripple current. With each converter operating
180° out of phase, the RMS currents add in the following
fashion:
which for the dual 3A converters of Figure 5, calculates to:
Power MOSFET Selection
Losses in a MOSFET are the sum of its switching (P
SW
) and
conduction (P
COND
) losses.
In typical applications, the FAN5236 converter’s output volt-
age is low with respect to its input voltage, therefore the
Lower MOSFET (Q2) is conducting the full load current for
most of the cycle. Q2 should therefore be selected to mini-
mize conduction losses, thereby selecting a MOSFET with
low R
DS(ON)
.
In contrast, the high-side MOSFET (Q1) has a much shorter
duty cycle, and it’s conduction loss will therefore have less
of an impact. Q1, however, sees most of the switching losses,
so Q1’s primary selection criteria should be gate charge.
High-Side Losses:
Figure 15 shows a MOSFET’s switching interval, with the
upper graph being the voltage and current on the Drain to
Source and the lower graph detailing V
GS
vs. time with a
constant current charging the gate. The x-axis therefore is
also representative of gate charge (Q
G
) . C
ISS
= C
GD
+ C
GS
,
and it controls t1, t2, and t4 timing. C
GD
receives the current
from the gate driver during t3 (as V
DS
is falling). The gate
charge (Q
G
) parameters on the lower graph are either
specified or can be derived from MOSFET datasheets.
Assuming switching losses are about the same for both the
rising edge and falling edge, Q1’s switching losses, occur
during the shaded time when the MOSFET has voltage
across it and current through it.
ESR
V
I
-------
<
(13)
V
OUT
8
F
SW
×
C
=
(14)
I
REG1
I
VDDQ
I
2
-----------
+
=
I
RMS
I
OUT MAX
)
D
D
2
=
(15)
D
V
IN
-V
<
16
=
(16)
I
RMS
3.5
16
16
2.5
2
1.49A
=
=
(17)
I
RMS
I
RMS 1
( )
2
I
RMS 2
( )
2
+
or
=
(18a)
I
RMS
I
1
(
)
2
D
1
D
1
2
(
)
I
2
(
)
2
D
2
D
2
2
(
)
+
=
(18b)
I
RMS
1.4A
=
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