參數(shù)資料
型號: FAN5240QSCX
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: Multi-Phase PWM Controller for AMD Mobile Athlon TM and Duron TM
中文描述: SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO28
封裝: QSOP-28
文件頁數(shù): 15/19頁
文件大?。?/td> 447K
代理商: FAN5240QSCX
PRODUCT SPECIFICATION
FAN5240
REV. 1.1.7 8/29/02
15
High-Side Losses:
Figure 12. Switching losses and Q
G
Figure 13. Drive Equivalent Circuit
Assuming switching losses are about the same for both the
rising edge and falling edge, Q1’s switching losses, as can be
seen by Figure 12, are given by:
where
R
DS(ON)
is @T
J(MAX)
and:
t
S
is the switching period (rise or fall time) and is predomi-
nantly the sum of t2, t3 (Figure 12), a function of the imped-
ance of the driver and the Q
G(SW)
of the MOSFET. Since
most of t
S
occurs when V
GS
= V
SP
we can use a constant
current assumption for the driver to simplify the calculation
of t
S
:
For the high-side MOSFET, V
DS
= VIN, which can be as
high as 20V in a typical portable application. Q2, however,
switches on or off with its parallel shottky diode conducting,
therefore V
DS
0.5V. Since P
SW
is proportional to V
DS
,
Q2's switching losses are negligible and we can select Q2
based on R
DS(ON)
only.
Care should also be taken to include the delivery of the
MOSFET's gate power ( P
GATE
)
in calculating the power
dissipation required for the FAN5240:
Low-Side Losses
Conduction losses for Q2 are given by:
where R
DS(ON)
is the R
DS(ON)
of the MOSFET at the
highest operating junction temperature and
is
the minimum duty cycle for the converter. Since D
MIN
is 5%
for portable computers, (1-D)
1, further simplifying the
calculation.
The maximum power dissipation (P
D(MAX)
) is a function of
the maximum allowable die temperature of the low-side
MOSFET, the
θ
J-A
, and the maximum allowable ambient
temperature rise:
θ
J-A
, depends primarily on the amount of PCB area that can
be devoted to heat sinking (see FSC app note AN-1029 for
SO-8 MOSFET thermal information).
V
SP
V
TH
t1
t2
t3
4.5V
t4
t5
Q
G(SW)
V
DS
I
D
Q
GS
Q
GD
V
GS
C
ISS
C
RSS
C
ISS
C
ISS
= C
GS
|| C
GD
C
GD
R
D
R
GATE
C
GS
19
HDRV
5V
20
SW
VIN
G
P
UPPER
P
SW
P
COND
+
=
(15a)
P
SW
V
---------------------
I
L
×
2
×
t
S
×
F
SW
=
(15b)
P
COND
V
IN
--------------
I
OUT
2
×
R
DS ON
)
×
=
(15c)
t
S
Q
DRIVER
)
--------------------
Q
DRIVER
GATE
------------------------+
---------------------------–
=
(16)
P
GATE
Q
G
VDD
F
SW
×
×
=
(17)
P
COND
1
D
(
)
I
OUT
2
×
R
DS ON
)
×
=
(18)
D
V
IN
--------------
=
P
D MAX
)
T
------------------------------------------------
T
)
J
A
=
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