PRODUCT SPECIFICATION
FAN53168
REV. 1.0.0 6/9/03
13
General Description and Applications Information
Theory of Operation
The FAN53168 combines a multi-mode,
fi
xed frequency
PWM control with multi-phase logic outputs for use in 2, 3
and 4 phase synchronous buck CPU core supply power con-
verters. The internal 6-bit VID DAC conforms to Intel
’
s
VRD/VRM 10 speci
fi
cations. Multi-phase operation is
important for producing the high currents and low voltages
demanded by today
’
s microprocessors. Handling the high
currents in a single-phase converter would place high ther-
mal demands on the components in the system such as the
inductors and MOSFETs.
The multi-mode control of the FAN53168 ensures a stable,
high performance topology for:
Balancing currents and thermals between phases
High speed response at the lowest possible switching
frequency and output decoupling
Minimizing thermal switching losses due to lower
frequency operation
Tight load line regulation and accuracy
High current output from having up to 4 phase operation
Reduced output ripple due to multi-phase cancellation
PC board layout noise immunity
Ease of use and design due to independent component
selection
Flexibility in operation for tailoring design to low cost or
high performance
Number of Phases
The number of operational phases and their phase relation-
ship is determined by internal circuitry which monitors the
PWM outputs. Normally, the FAN53168 operates as a 4-
phase PWM controller. Grounding the PWM4 pin programs
3-phase operation, and grounding the PWM3 and PWM4
pins programs 2-phase operation.
When the FAN53168 is enabled, the controller outputs a
voltage on PWM3 and PWM4 that is approximately 550 mV.
An internal comparator checks each pin’s voltage versus a
threshold of 400mV. If the pin is grounded, then it will be
below the threshold and the phase will be disabled. The out-
put impedance of the PWM pin is approximately 5k
. Any
external pull-down resistance connected to the PWM pin
should not be less than 25k
to ensure proper operation. The
phase detection is made during the first 2 clock cycles of the
internal oscillator. After this time, if the PWM output was
not grounded, then it will switch between 0V and 5V. If the
PWM output was grounded, then it will remain off.
The PWM outputs become logic-level devices once normal
operation starts. The detection is normal and is intended for
driving external gate drivers, such as the FAN53418. Since
each phase is monitored independently, operation approach-
ing 100% duty cycle is possible. Also, more than one output
can be on at a time for overlapping phases.
Master Clock Frequency
The clock frequency of the FAN53168 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in TPC 1. To determine the frequency per
phase, the clock is divided by the number of phases in use.
If PWM4 is grounded, then divide the master clock by 3 for
the frequency of the remaining phases. If PWM3 and 4 are
grounded, then divide by 2. If all phases are in use, divide
by 4.
Output Voltage Differential Sensing
The FAN53168 combines differential sensing with a high
accuracy VID DAC and reference and a low offset error
ampli
fi
er to maintain a worst-case speci
fi
cation of ±10 mV
differential sensing error with a VID input of 1.6000 V over
its full operating output voltage and temperature range. The
output voltage is sensed between the FB and FBRTN pins.
FB should be connected through a resistor to the regulation
point, usually the remote sense pin of the microprocessor.
FBRTN should be connected directly to the remote sense
ground point. The internal VID DAC and precision reference
are referenced to FBRTN, which has a minimal current of
90μA to allow accurate remote sensing. The internal error
ampli
fi
er compares the output of the DAC to the FB pin to
regulate the output voltage.
Output Current Sensing
The FAN53168 provides a dedicated current sense ampli
fi
er
(CSA) to monitor the total output current for proper voltage
positioning versus load current and for current limit detec-
tion. Sensing the load current at the output gives the total
average current being delivered to the load, which is an
inherently more accurate method then peak current detection
or sampling the current across a sense element such as the
low side MOSFET. This ampli
fi
er can be con
fi
gured several
ways depending on the objectives of the system:
Output inductor ESR sensing without thermistor for
lowest cost
Output inductor ESR sensing with thermistor for
improved accuracy with tracking of inductor temperature
Sense resistors for highest accuracy measurements
The positive input of the CSA is connected to the CSREF
pin, which is connected to the output voltage. The inputs to
the ampli
fi
er are summed together through resistors from the
sensing element (such as the switch node side of the output
inductors) to the inverting input, CSSUM. The feedback
resistor between CSCOMP and CSSUM sets the gain of the
ampli
fi
er, and a
fi
lter capacitor is placed in parallel with this
resistor. The gain of the ampli
fi
er is programmable by adjust-
ing the feedback resistor to set the load line required by the
microprocessor. The current information is then given as the
difference of CSREF
–
CSCOMP. This difference signal is
used internally to offset the VID DAC for voltage positioning
and as a differential input for the current limit comparator.