參數(shù)資料
型號： FAN5355UC07X
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 穩(wěn)壓器
英文描述： 1.8 A SWITCHING CONTROLLER, 3350 kHz SWITCHING FREQ-MAX, PBGA12
封裝： 2.23 X 1.46 MM, 0.50 MM PITCH, GREEN, WLCSP-12
文件頁數(shù)： 9/27頁
文件大小： 1995K
代理商： FAN5355UC07X
2008 Fairchild Semiconductor Corporation
17
www.fairchildsemi.com
FAN5355 Rev. 1.0.4
FA
N
5355
—
1A
/
0.8A
,3M
hz.
D
igit
a
lly
Prog
rammabl
e
TinyB
u
ck
TM
Regulator
Circuit Description
Overview
The FAN5355 is a synchronous buck regulator that typically
operates at 3MHz with moderate to heavy load currents. At
light load currents, the converter operates in power-saving
PFM mode. The regulator automatically transitions between
fixed-frequency PWM and variable-frequency PFM mode to
maintain the highest possible efficiency over the full range of
load current.
The FAN5355 uses a very fast non-linear control architecture
to achieve excellent transient response with minimum-sized
external components.
The FAN5355 integrates an I
2C-compatible interface, allowing
transfers up to 3.4Mbps. This communication interface can be
used to:
1.
Dynamically re-program the output voltage in 12.5mV
increments.
2.
Reprogram the mode of operation to enable or disable
PFM mode.
3.
Control voltage transition slew rate.
4.
Control the frequency of operation by synchronizing to an
external clock.
5.
Enable / disable the regulator.
For more details, refer to the I
2C Interface and Register
Description sections.
Output Voltage Programming
Option
VOUT Equation
00, 02,
03
mV
5
.
12
N
75
.
0
V
VSEL
OUT
+
=
(1)
07
mV
25
N
100
.
0
V
VSEL
OUT
+
=
for NVSEL = 0 to 23
(
)
mV
5
.
12
23
N
675
.
0
V
VSEL
OUT
+
=
for NVSEL > 23
(2)
06
mV
5
.
12
N
1875
.
1
V
VSEL
OUT
+
=
(3)
where NVSEL is the decimal value of the setting of the VSEL
register that controls VOUT.
Note:
13. Option 02 maximum voltage is 1.4375V (see Table 3).
Power-up, EN, and Soft-start
All internal circuits remain de-biased and the IC is in a very
low quiescent current state until the following are true:
1.
VIN is above its rising UVLO threshold, and
2.
EN is HIGH.
At that point, the IC begins a soft-start cycle, its I
2C interface is
enabled, and its registers loaded with their default values.
During the initial soft-start, VOUT ramps linearly to the setpoint
programmed in the VSEL register selected by the VSEL pin.
The soft start features a fixed output voltage slew rate of
18.75V/ms, and achieves regulation approximately 90
μs after
EN rises. PFM mode is enabled during soft-start until the
output is in regulation, regardless of the MODE bit settings.
This allows the regulator to start into a partially charged output
without discharging it; in other words, the regulator does not
allow current to flow from the load back to the battery.
As soon as the output has reached its setpoint, the control
forces PWM mode for about 85
μs to allow all internal control
circuits to calibrate.
Symbol Description
Value (
μs)
tSSDLY
Time from EN to start of
soft-start ramp
25
Opt 06
16 +(VSEL–0.7) X 53
tREG
VOUT ramp start to
regulation
Others
(VSEL–0.1) X 53
tPOK
PWROK (CONTROL2[5])
rising from tREG
11
tCAL
Regulator stays in PWM
mode during this time
10
Table 2. Soft-Start Timing (see Figure 35)
VOUT
0
EN
PWROK
T
REG
VSEL
T
POK
T
CAL (FPWM)
T
SSDLY
Figure 35. Soft-start Timing
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