參數(shù)資料
型號(hào): FAN6921MLMY
廠商: Fairchild Semiconductor
文件頁(yè)數(shù): 5/23頁(yè)
文件大?。?/td> 1764K
描述: IC CTLR PFC/FLYBACK 16-SOICN
標(biāo)準(zhǔn)包裝: 2,500
模式: 臨界傳導(dǎo)(CRM)
電流 - 啟動(dòng): 10µA
電源電壓: 8.5 V ~ 25 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC N
包裝: 帶卷 (TR)
 
?2010 Fairchild Semiconductor Corporation
 
www.fairchildsemi.com
FAN6921ML " Rev. 1.0.3
5
Pin Definitions
Pin #   Name   Description
6
OPFC
otem-pole driver output to drive the external power MOSFET. The clamped gate output voltage is
15.5 V.
7
VDD
Power supply. The threshold voltages for startup and turn-off are 18 V and 7.5 V, respectively. The
tartup current is less than 30 礎(chǔ) and the operating current is lower than 10mA.
8
OPWM
otem-pole output generates the PWM signal to drive the external power MOSFET. The clamped
ate output voltage is 17.5 V.
9
GND
he power ground and signal ground.
10
DET
his pin is connected to an auxiliary winding of the PWM transformer through a resistor divider for
he following purposes:
? Producing an offset voltage to compensate the threshold voltage of PWM current limit for
providing over-power compensation. The offset is generated in accordance with the input
voltage when PWM switch is on.
? Detecting the valley voltage signal of drain voltage of the PWM switch to achieve the valley
voltage switching and minimize the switching loss on the PWM switch.
? Providing output over-voltage protection. A voltage comparator is built-in to the DET pin. The
DET pin detects the flat voltage through a voltage divider paralleled with auxiliary winding. This
flat voltage is reflected to the secondary winding during PWM inductor discharge time. If output
OVP and this flat voltage is higher than 2.5 V, the controller enters latch mode and stops all
PFC and PWM switching operation.
11
FB
Feedback voltage pin. This pin is used to receive the output voltage level signal to determine PWM
ate duty for regulating output voltage. The FB pin voltage can also activate open-loop, overload,
r output-short-circuit protection if the FB pin voltage is higher than a threshold of around 4.2 V for
more than 50 ms. The input impedance of this pin is a 5 k?equivalent resistance. A 1/3 attenuator
is connected between the FB pin and the input of the CSPWM/FB comparator.
12
RT
djustable over-temperature protection and external latch triggering. A constant current flows out
f the RT pin. When RT pin voltage is lower than 0.8 V (typical), latch mode protection is activated
nd stops all PFC and PWM switching operation until the AC plug is removed.
13
VIN
Line-voltage detection for brownin/out protections. This pin can receive the AC input voltage level
hrough a voltage divider. The voltage level of the VIN pin is not only used to control RANGE pins
tatus, but it can also perform brownin/out protection for AC input voltage UVP.
14
ZCD
ero-current detection for the PFC stage. This pin is connected to an auxiliary winding coupled to
PFC inductor winding to detect the ZCD voltage signal once the PFC inductor current discharges
o zero. When the ZCD voltage signal is detected, the controller starts a new PFC switching cycle.
hen the ZCD pin voltage is pulled to under 0.2 V (typical), it disables the PFC stage and the
ontroller stops PFC switching. This can be realized with an external circuit if disabling the PFC
tage is desired.
15
NC
No connection
16
HV
High-voltage startup. HV pin is connected to the AC line voltage through a resistor (100 k?typical)
or providing a high-charging current to V
DD
 capacitor.
 
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