參數(shù)資料
型號(hào)： FAN6982MY
廠商： Fairchild Semiconductor
文件頁(yè)數(shù)： 12/16頁(yè)
文件大?。?/td> 547K
描述： IC CTLR PFC CCM 14-SOICN
標(biāo)準(zhǔn)包裝： 2,500
模式： 連續(xù)導(dǎo)電（CCM）
頻率 - 開(kāi)關(guān)： 50kHz ~ 75kHz
電流 - 啟動(dòng)： 30µA
電源電壓： 11 V ~ 22 V
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 14-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC N
包裝： 帶卷 (TR)
 
?2009 Fairchild Semiconductor Corporation
 
www.fairchildsemi.com
FAN6982 " Rev. 1.0.3
12
Functional Description
Oscillator
The   internal   oscillator   frequency   of   FAN6982   is
determined by the timing resistor and capacitor on the
RT/CT pin, but note that the optimum operation for
FAN6982 is between 50 and 75kHz. The frequency of
the internal oscillator is given by:
1
0.56
360
OSC
T
T
T
f
C
C
=
?nbsp  ?nbsp   +
 
 (1)
The dead time for the PFC gate drive signal is
determined by
360
DEAD
T
t
C
=
 
 (2)
The dead time should be smaller than 2% of switching
period to minimize line current distortion around line
zero crossing.
Gain Modulator
Gain modulator is the key block for PFC stage because
it provides the reference to the current control error
amplifier for the input current shaping, as shown in
Figure 23. The output current of gain modulator is a
function of V
EA
, I
AC
  and V
RMS
. The gain of the gain
modulator is given as a ratio between I
MO
 and I
AC
 with a
given V
RMS
 when V
EA
 is saturated to high. The gain is
inversely proportional to V
RMS
2
, as shown in Figure 24,
to   implement   line   feed-forward.   This   automatically
adjusts the reference of current control error amplifier
according to the line voltage such that the input power
of PFC converter is not changed with line voltage, as
shown in, Figure 25.
=    ?/DIV>
?/DIV>

=
?/DIV>

2
(
0.6)
(
0.6)
MO
AC
EA
AC
MAX
RMS
EA
I
G  I
K   V
I
V
V
 
Figure 23. Gain Modulator Block
V
RMS
V
RMS-UVP
2
1
RMS
G
V

 
Figure 24. Modulation Gain Characteristics
V
IN
I
L
V
EA
 
Figure 25. Line Feed-Forward Operation
To sense the RMS value of the line voltage, an
averaging circuit with two poles is typically employed as
shown in Figure 23. Notice that the input voltage of
PFC is clamped at the peak of the line voltage once
PFC stops switching since the junction capacitance of
bridge diode is not discharged, as shown in Figure 26.
Therefore, the voltage divider for V
RMS
  should be
designed considering the brownout protection trip point
and minimum operation line voltage.
PFC runs
PFC stops
V
IN
V
RMS
 
Figure 26. V
RMS
 According to the PFC Operation
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