參數(shù)資料
型號: FAN8048
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 運(yùn)動(dòng)控制電子
英文描述: 2 DC-DC Converter & 4-CH PWM Motor IC
中文描述: DISK DRIVE MOTOR CONTROLLER, 0.5 A, PDSO48
封裝: 7 X 7 MM, LQFP-48
文件頁數(shù): 24/34頁
文件大?。?/td> 903K
代理商: FAN8048
FAN8048
24
3.11 Component of Error Amplifier Compensation Network
In this chapter, we would like discuss the method of converter error amplifier design to control voltage mode PWM. In general,
a negative feedback control circuit composed of error amplifier using an operational amplifier and comparator is often used to
stabilize output voltage in switching mode converters. Controller design standards and methods for a stable system are as fol-
lows:
(1) To reduce regulation error of the output voltage, the loop gain crossover frequency, f
C,
should be as high as possible.
(2) To obtain stable phase margin, let the slope gain at 0dB be -20dB/dec. That is, have the gain phase at 0dB close to -90°.
(3) Set the loop gain crossover frequency, f
C
be set to 1/5 ~ 1/10 of the switching frequency f
S
.
But in boost converter, due to the RHP zero, f
RHPZ
, the loop gain frequency, fC, must be designed well below the RHP
zero because the boost converter have a right half plane (RHP) zero. ( f
C
=f
RHPZ
/10)
(4) Set compensation pole, f
P1
to cancel the ESR zero f
FILTER_ZERO
. (f
P1
= f
FILTER_ZERO
)
(5) Place a high-frequency compensator pole, f
P2
to get the maximum attenuation of the switching ripple and high frequency
noise the minimum phase lag at f
C
.
(6) Place a two compensator zeroes, f
Z1
and f
Z2
below f
C
. Place the fz1 below the power stage natural frequency,
f
FILTER_POLE
to avoid a conditional stability. When setting these two zeroes (fz1 and fz2), converter performance and sta-
bility margin should be considered.
(7) Select the compensator parameters. (R’s and C’s )
To meet the design standards mentioned above, Figure 18 shows circuits and the characteristics of a typical compensator,
which has a controller structure with two zeroes (fz1 and fz2) and poles (fp1 and fp2).
First of all to design an error amplifier, natural frequency of system, f
FILTER_POLE
and ESR zero using an equivalent series
resistance of the output capacitor can be obtained by the following formula.
Double poles by the output filter are obtained from the following formula:
Where, Co is the output capacitor.
The ESR zero by the output capacitor, C
O
and equivalent series resistance of the output capacitor, R
ESR
can be obtained by the
following formula.
where, R
ESR
is the equivalent series resistance of output filter capacitor.
Figure 18. Error Amplifier Compensation Circuit
]
[
2
1
_
Hz
LC
f
O
POLE
FILTER
π
=
]
[
2
1
_
Hz
C
R
f
O
ESR
ZERO
FILTER
×
×
=
π
Phase
Gain
-20dB/dec
= -2slop
-20dB/dec
= -2slop
20dB/dec
= +2slop
+90
o
-90
o
0
o
Av1
Av2
f1
f2
f3
f4
VSYS
R1
R4
C1
11
10
0.9V
Error Amp
R2
R3
C3
C2
Note
C
>>C
3
R1>>R3
Vc
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