參數(shù)資料
型號: FIN1002M5
廠商: Fairchild Semiconductor
文件頁數(shù): 1/7頁
文件大?。?/td> 0K
描述: RECEIVER 3.3V LVDS HS SOT-23
產(chǎn)品變化通告: Mold Compound Change 12/Dec/2007
Product Discontinuation 14/Mar/2011
標(biāo)準(zhǔn)包裝: 250
類型: 接收器
驅(qū)動器/接收器數(shù): 0/1
規(guī)程: LVDS
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: SC-74A,SOT-753
供應(yīng)商設(shè)備封裝: SOT-23-5
包裝: 管件
2002 Fairchild Semiconductor Corporation
DS500730
www.fairchildsemi.com
February 2002
Revised February 2002
FI
N1002
L
V
DS
1-
Bit
Hi
gh
Speed
Dif
fe
rent
ial
Rece
iver
FIN1002
LVDS 1-Bit High Speed Differential Receiver
General Description
This single receiver is designed for high speed intercon-
nects utilizing Low Voltage Differential Signaling (LVDS)
technology. The receiver translates LVDS levels, with a typ-
ical differential input threshold of 100 mV, to LVTTL signal
levels. LVDS provides low EMI at ultra low power dissipa-
tion even at high frequencies. This device is ideal for high
speed transfer of clock or data.
The FIN1002 can be paired with its companion driver, the
FIN1001, or with any other LVDS driver.
Features
s Greater than 400Mbs data rate
s 3.3V power supply operation
s 0.4ns maximum pulse skew
s 2.5ns maximum propagation delay
s Bus pin ESD (HBM) protection exceeds 10kV
s Power-Off over voltage tolerant input and output
s Fail safe protection for open-circuit and non-driven,
shorted or terminated conditions
s High impedance output at VCC < 1.5V
s Meets or exceeds the TIA/EIA-644 LVDS standard
s 5-Lead SOT23 package saves space
Ordering Code:
Pin Descriptions
Function Table
H
= HIGH Logic Level
L
= LOW Logic Level
Fail Safe
= Open, Shorted, Terminated
Connection Diagram
Pin Assignment for SOT package
Top View
Order Number
Package Number
Package Description
FIN1002M5
MA05B
5-Lead SOT23, JEDEC MO-178, 1.6mm [250 Units on Tape and Reel]
FIN1002M5X
MA05B
5-Lead SOT23, JEDEC MO-178, 1.6mm [3000 Units on Tape and Reel]
Pin Name
Description
ROUT
LVTTL Data Output
RIN+
Non-inverting Driver Input
RIN
Inverting Driver Input
VCC
Power Supply
GND
Ground
NC
No Connect
Input
Outputs
RIN+
RIN
ROUT
LH
L
HL
H
Fail Safe Condition
H
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