參數(shù)資料
型號： FIN212ACGFX
廠商： Fairchild Semiconductor
文件頁數(shù)： 10/16頁
文件大?。?/td> 0K
描述： IC SER/DESER 12BIT 42USS-BGA
標(biāo)準(zhǔn)包裝： 1
系列： SerDes™
功能： 串行器/解串器
數(shù)據(jù)速率： 560Mbps
輸入類型： LVCMOS
輸出類型： LVCMOS
輸入數(shù)： 12
輸出數(shù)： 12
電源電壓： 1.65 V ~ 3.6 V
工作溫度： -30°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 42-VFBGA
供應(yīng)商設(shè)備封裝： 42-BGA
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 1216 (CN2011-ZH PDF)
其它名稱： FIN212ACGFXDKR
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN212AC Rev. 1.1.1
3
S
erDe
s
FIN212
AC
—
12
-Bit
Se
rial
izer
/
De
seriali
zer
Suppo
rti
ng
Ca
meras
and
Small
Displays
FIN212AC (Deserializer DIRI=0) Pin Descriptions
Pin Name
Description
DIRI
Control to determine serializer or deserializer configuration.
0
Deserializer
1
Serializer
XTERM
Control to determine if using internal or external termination
0
Internal termination used
1
External termination required on CKSI & DSI
S0
Signals used to define the edge rate of parallel I/O.
See Table 2 Deserializer (DIRI=0) Control Pin.
S1
Signals used to define the edge rate of parallel I/O.
See Table 2 Deserializer (DIRI=0) Control Pin.
PWS0
Configure CKP pulse width.
See Table 2 Deserializer (DIRI=0) Control Pin.
PWS1
Configure CKP pulse width.
See Table 2 Deserializer (DIRI=0) Control Pin.
DP[1:12]
LV-CMOS parallel data output. (N/C if not used)
CKP
LV-CMOS word clock output or Pixel clock output.
DSI+
DSI-
CTL Differential serial input data signals.
DSI+: Positive signal; DSI-: Negative signal.
CKSI+
CKSI-
CTL Differential deserializer input bit clock.
CKSI+: Positive signal; CKSI-: Negative signal.
CKSO+
CKSO-
CTL Differential serializer output bit clock.
CKSO+: Positive signal; CKSO-: Negative signal.
No connect unless in “clock pass-through” mode.
CKREF
LV-CMOS clock input and PLL reference.
No connect unless in “clock pass-through” mode.
STROBE
LV-CMOS strobe input for latching data into the serializer.
No connect unless in
“clock pass-through” mode.
/DIRO
LV-CMOS Output. Inversion of DIRI in normal operation.
No connect if not used.
VDDP
Power supply for parallel I/O. (All VDDP pins must be connected to VDDP)
VDDS
Power supply for serial I/O.
VDDA
Power supply for core.
GND
All GND pins must be connected to ground. BGA: all GND pads. MLP: Pin 28, 29, GND PAD must be grounded.
N/C
No connect. BGA: G1, F2; MLP: 10, 11; (Do not connect to GND or VDD)
Note:
2.
0=GND; 1=VDDP
FIN212AC (Deserializer DIRI=0) Pin Configurations
GND
DP[2]
CKREF
DP[5]
DP[1]
STROBE
DP[3]
VDDP
GND
PWS1
1
A
3
4
5
6
2
B
C
D
E
F
G
DP[4]
DP[6]
/DIRO
CKP
CKSO+
CKSO-
DP[7]
DSI+
DSI-
DP[8]
DP[9]
VDDS
CKSI+
CKSI-
DP[10]
VDDA
DIRI
PWS0
S1
S0
GND
N/C
DP[11]
DP[12]
XTRM
N/C
12
13
14
15
31
30
28
27
26
25
DESERIALIZER
GND PAD
DP[4]
CKSO+
CKSO-
DSI-
DSI+
CKSI-
CKSI+
DIRI
VDDS
DP[
3]
DP[
2]
DP[
1]
GND
STR
OBE
CKR
EF
/DIRO
PW
S
1
PW
S
0
S1
S0
VDD
A
1
DP[5] 2
4
DP[6]
VDDP
3
CKP 5
DP[7] 6
DP[8] 7
DP[9] 8
9
DP[
10
]
32
20
21
19
23
18
16
17
22
24
29
X
TR
M
10
DP[
11
]
11
DP[
12
]
32-pin MLP, 5mm x 5mm, .5mm pitch (Top View)
Figure 3. FIN212AC (Deserializer DIRI=0) Pin Assignments (Top View)
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