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| 型號(hào)： | FLASHMEMORYPRODUCTSELECTORGUIDE |
| 英文描述： | --(35.00 k) |
| 中文描述： | - （35.00十一） |
| 文件頁(yè)數(shù)： | 2/2頁(yè) |
| 文件大小： | 201K |
| 代理商： | FLASHMEMORYPRODUCTSELECTORGUIDE |
Flash Card Controller Requirements
The controller manages the storage of data on the card and han-
dles communication between the card and the host. It receives
data from the host and writes it to the bank of flash memory. It
responds to requests for data by reading from the memory bank
and passing data to the host. The host interface is defined by the
ATA/ IDE interface or the PC Card II/CompactFlash Services.
Support Interfaces.
To ensure that the data is correct the controller uses ECC (Error
Checking and Correction). During write operations, a calcula-
tion on the data to be stored generates additional code bytes.
These are stored with the original data in the flash memory
bank and, during read operations, are used in a reverse calcula-
tion to validate the data and correct bit errors.
After multiple read-write operations, individual bits in flash
memory can deteriorate. Optimal card life requires equal use
of each bit and “wear-levelling” algorithms, executed on the fly
during reading and writing operations, have been developed to
provide this.
Design Options
Since both ECC and wear-levelling
are carried out on the fly, a flash
card controller has to be able to
carry out these tasks at speeds
that match the operational speeds
of the host device.
A controller designed for a specific
card and manufactured in volume
could be implemented as an ASIC.
But if it is to have more general
application then the ASIC has lim-
itations. It needs to be able to
cope with different flash memory
devices with different characteris-
tics and different wear-levelling
requirements, with improved ECCs
and with different host interfaces.
Hyperstone has implemented the
F1-8X, a powerful single-chip con-
troller solution as an ASSP (Appli-
cation Specific Standard Product).
Based on the Hyperstone com-
bined RISC/DSP processor it is
a high-speed, low-power, flexible
solution for a wide range of flash
card applications, up to 992
MBytes and beyond.
The Design Solution
The 32-bit Hyperstone F1-8X ASSP implements
complete flash card functionality in a single chip
programmable device. (see diagram)
The external 16 bit wide interface to the host
device supports both ATA Flash Memory cards
and CompactFlash cards. It is in full compli-
ance with the PCMCIA standards and has the
option of a True-IDE mode. The interface pro-
vides automatic selection of either 5.0V or 3.3V
power supply.
Once data has crossed the host interface, it is
passed to the flash memory interface where a
firmware implementation of the sophisticated 32
polynomial Error Correction Code algorithm gen-
erates the check bytes. During both write and
read operations, the Hyperstone implemented
ECC has no overheads.
The flash memory interface provides full support
for up to 16 memory devices from AMD, Hitachi,
Mitsubishi, Samsung, Toshiba and other compat-
ible manufacturers providing up to 992 MBytes
of storage. It can achieve transfer rates of up
to 20Mbytes/sec. It also incorporates a voltage
regulator to provide the 3.3V supply needed
for flash.
The wear-levelling algorithm is executed in the
RISC core. The F1-8X device uses an extremely
sophisticated algorithm, developed by Hyper-
stone and now being patented, which equalises the
use of all locations for optimal card life. It supports the
wear characteristics of a wide range of different man-
ufactures devices. Since the wear-levelling algorithm
is in software, the F1-8X device will be able to sup-
port new memories with different wear characteristics
with only minor code changes. Card life will exceed
100,000,000 write cycles with a MTBF in excess of
1,000,000 hours.
The 4 KByte Boot ROM holds the flash memory access
routines. It also has the routines for loading the oper-
ational code into the internal 16 KByte RAM of the
controller from the first memory areas of the flash
memory, where it is stored during manufacture. The on-
chip RAM is also used for intermediate storage during
wear levelling calculations. Internal memory reduces
overall component count and improves start-up and
run-time performance.
Typical power requirements are 29mA for reading to
memory and 28mA for writing. Idle mode power con-
sumption is 5mA (typical) while in sleep mode the con-
troller requires 100μA (typical).
Applications and Availability
To meet different applications, Hyperstone provides a
design kit and a range of products based on the F1-8X
device to meet different application requirements.
0
500
1000
Transfer Speed (KByte/sec)
1500
2000
2500
3000
Hyperstone
Manufacturer M
Manufacturer L
Manufacturer H
Manufacturer S
0
20
40
60
80
100
Hyperstone
Manufacturer M
Manufacturer L
Manufacturer H
Manufacturer S
Random Read Time (ms)
0
50
100
150
200
250
Hyperstone
Manufacturer M
Manufacturer L
Manufacturer H
Manufacturer S
Random Write Time (ms)
0
30
60
90
120
150
Hyperstone
Manufacturer M
Manufacturer L
Manufacturer H
Manufacturer S
Weighted Average Time (ms)
Source: Hyperstone benchmarking using QBENCH from Quantum Data
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