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  • 參數(shù)資料
    型號: FM2540-7PD3AH
    元件分類: 電源模塊
    英文描述: 2-OUTPUT 50 W DC-DC REG PWR SUPPLY MODULE
    封裝: METAL, CASE M02, MODULE
    文件頁數(shù): 15/25頁
    文件大?。?/td> 569K
    代理商: FM2540-7PD3AH
    Cassette Style
    DC-DC Converters
    M Series
    Edition 01/01.2001
    22/25
    0
    1
    0.95
    0
    U
    i [V DC]
    0
    t
    low min
    4
    t
    low min
    4
    t
    high min
    t
    h
    1
    U
    ti +Uhi
    U
    ti
    Input voltage failure
    Switch-on cycle
    Input voltage sag
    Switch-on cycle and subsequent
    input voltage failure
    U
    D high
    U
    D low
    U
    D
    0
    JFET
    NPN
    t
    U
    o1
    U
    o1 nom
    U
    D high
    U
    D low
    U
    D
    t
    low min
    4
    t
    h
    1
    0
    U
    D high
    U
    D low
    U
    D
    0
    JFET
    NPN
    U
    o1
    U
    D high
    U
    D low
    U
    D
    t
    low min
    4
    U
    to
    3
    Output voltage failure
    0
    I
    D high
    I
    D low
    I
    D
    t
    0
    I
    D high
    I
    D low
    I
    D
    t
    3
    2
    33
    U
    o1 nom
    U
    to +Uho
    Input voltage monitoring
    Output voltage monitoring
    11008
    Threshold tolerances and hysteresis:
    If
    Ui is monitored, the internal input voltage after the input
    filter and rectifier (EM, LM and LMZ types) is measured.
    Consequently this voltage differs from the voltage at the
    connector pins by the voltage drop
    DUti across input filter
    and rectifier. The threshold level of the D0 and D9 options is
    factory adjusted at nominal output current
    Io nom and at TA =
    25
    °C. The value of DU
    ti depends upon the input voltage
    range (AM, BM, ...), threshold level
    Ut, temperature and in-
    put current. The input current is a function of the input volt-
    age and the output power.
    Fig. 24
    Relationship between Ui, Uo1, UD, ID and Uo1/Uo nom versus time.
    DUti
    Uhi
    UD low
    UD
    UD high
    Ui
    P
    o
    =
    P
    o
    nom
    P
    o
    =
    0
    P
    o
    =
    0
    Uti
    P
    o
    =
    P
    o
    nom
    11021
    Fig. 23
    Definition of Uti, DUti and Uhi (JFET output)
    1 See: Electrical Output Data, for hold-up time.
    2 With output voltage monitoring the hold-up time th = 0
    3 The D signal remains high if the D output is connected to
    an external source.
    4 tlow min = 40...200 ms, typically 80 ms
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