FM3104/16/64/256
Rev 0.21
Nov 2003
Page 16 of 22
Memory Read Operation
There are two types of memory read operations. They
are current address read and selective address read. In
a current address read, the FM31xxx uses the internal
address latch to supply the address. In a selective
read, the user performs a procedure to first set the
address to a specific value.
Current Address & Sequential Read
As mentioned above the FM31xxx uses an internal
latch to supply the address for a read operation. A
current address read uses the existing value in the
address latch as a starting place for the read
operation. The system reads from the address
immediately following that of the last operation.
To perform a current address read, the bus master
supplies a slave address with the LSB set to 1. This
indicates that a read operation is requested. After
receiving the complete device address, the FM31xxx
will begin shifting data out from the current address
on the next clock. The current address is the value
held in the internal address latch.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte the internal address counter
will be incremented.
Each time the bus master acknowledges a byte,
this indicates that the FM31xxx should read out
the next sequential byte.
There are four ways to terminate a read operation.
Failing to properly terminate the read will most likely
create a bus contention as the FM31xxx attempts to
read out additional data onto the bus. The four valid
methods follow.
1. The bus master issues a NACK in the 9
th
clock
cycle and a Stop in the 10
th
clock cycle. This is
illustrated in the diagrams below and is
preferred.
2. The bus master issues a NACK in the 9
th
clock
cycle and a Start in the 10
th
.
3. The bus master issues a Stop in the 9
th
clock
cycle.
4. The bus master issues a Start in the 9
th
clock
cycle.
If the internal address reaches the top of memory, it
will wrap around to 0000h on the next read cycle.
The figures below show the proper operation for
current address reads.
Selective (Random) Read
There is a simple technique that allows a user to
select a random address location as the starting point
for a read operation. This involves using the first
three bytes of a write operation to set the internal
address followed by subsequent read operations.
To perform a selective read, the bus master sends out
the slave address with the LSB set to 0. This specifies
a write operation. According to the write protocol,
the bus master then sends the address bytes that are
loaded into the internal address latch. After the
FM31xxx acknowledges the address, the bus master
issues a Start condition. This simultaneously aborts
the write operation and allows the read command to
be issued with the slave address LSB set to a 1. The
operation is now a read from the current address.
Read operations are illustrated below.
RTC/Companion Write Operation
All RTC and Companion writes operate in a similar
manner to memory writes. The distinction is that a
different device ID is used and only one byte address
is needed instead of two. Figure 16 illustrates a single
byte write to this device.
RTC/Companion Read Operation
As with writes, a read operation begins with the
Slave Address. To perform a register read, the bus
master supplies a Slave Address with the LSB set to
1. This indicates that a read operation is requested.
After receiving the complete Slave Address, the
FM31xxx will begin shifting data out from the
current register address on the next clock. Auto-
increment operates for the special function registers
as with the memory address. A current address read
for the registers look exactly like the memory except
that the device ID is different.
The FM31xxx contains two separate address
registers, one for the memory address and the other
for the register address. This allows the contents of
one address register to be modified without affecting
the current address of the other register. For example,
this would allow an interrupted read to the memory
while still providing fast access to an RTC register. A
subsequent memory read will then continue from the
memory address where it previously left off, without
requiring the load of a new memory address.
However, a write sequence always requires an
address to be supplied.