7
F
www.fairchildsemi.com
FM3580 Rev. A.5
Functional Description
(Continued)
SOPR-A/SOPR-B/PIPR Read Operation (Block)
Following is the SMBus command sequence to read from SOPR-
A, SOPR-B and PIPR registers in single command sequence. Read
operation starts with a valid
“
START
”
command, followed by device
address byte with Read-Write bit set to
“
1
”
. On receiving a valid
device address, FM3580 issues an
“
ACK
”
pulse. The device now
outputs a byte of data with a
“
byte count
”
value of 0x03h indicating
3 bytes of actual data are provided after this byte. Upon receiving
this byte count information, the system issues an
“
ACK
”
pulse. The
device now outputs a byte of data from SOPR-A register; upon
receiving this data byte, the system issues an
“
ACK
”
pulse. The
device continues to output a byte of data now from SOPR-B
register; upon receiving this data byte, the system issues an
“
ACK
”
pulse. The device finally outputs a byte of data from PIPR register;
upon receiving this data byte, the system stops the read operation
by issuing a
“
NO ACK
”
pulse. Refer Read VID Registers diagram.
Security Block
The security block forms the core of the anti-cloning protection. The
security block uses a 64-bit Seed data and a 16-bit Manufacturer ID
(MID) to compute a 64-bit pseudo-random code. The Seed data is
typically written into the FM3580 device by the BIOS during normal
operation. The MID is assigned by Fairchild and is unique to each
vendor and s permanently programmed nto the FM3580 by Fairchild.
Reading or Writing of the MID with respect to FM3580 is not possible.
Pseudo-random code generation
Every time the PC is cold booted, BIOS reads the 64-bit seed
information it wrote during previous normal operation and the 64-bit
pseudo-random code from the FM3580. Using the read 64-bit seed
information and the 16-bit MID, the BIOS computes and generates
the pseudo-random code. If both the
“
BIOS computed
”
code and
the
“
FM35800 read
”
code match, then the BIOS allows the PC to
boot. Otherwise, the BIOS alters the VID configuration so that the
PC is powered down. For example, the SOPR-B register can be set
with a VID value for NO CPU and then switching SOPR-B data to
Y-Port. On a successful boot-up, the BIOS can write a new seed
number into the FM3580 in order for the security code to be rolling.
Accessing Security Block
FM3580
’
s internal security block can be accessed via the SMBus
interface by using specific command bytes in the commands that
are issued to the device. SMBus operations to security block are
quite similar to VID block operations except the different com-
mand bytes ( register address
’
) are used. All SMBus accesses to
the security block are of block-read/write type. Following are the
supported commands.
Command Byte
Command Description
0xC0h
Write 64-bit Seed number
0xC1h
Read 64-bit Seed number
0xC3h
Read 64-bit Security code
Writing Seed Number
Writing the 64-bit Seed number is done as follows. Like all SMBus
command, a valid START condition starts the cycle, followed by
Device address byte with Read-Write bit set to
“
0
”
. On receiving
a valid device address FM3580 issues an
“
ACK
”
pulse. This is
followed by Write Seed number command byte (0xC0h) for which
FM3580 issues an
“
ACK
”
pulse. This is followed by Byte-count
byte (0x08h) indicating 8 bytes of Seed data will be sent. FM3580
issues an
“
ACK
”
pulse for the Byte-count byte. After this the
system issues 8 bytes of Seed data. For each byte thus received,
FM3580 issues an
“
ACK
”
pulse. After receiving the last ACK
pulse, the system issues a STOP condition at which point the write
operation begins internally. Refer Write Seed Number diagram.
Reading Seed Number
Reading the 64-bit Seed number is done as follows. Like all SMBus
command, a valid START condition starts the cycle, followed by
Device address byte with Read-Write bit set to
“
0
”
. On receiving a
valid device address FM3580 issues an
“
ACK
”
pulse. This is
followed by Read Seed number command byte (0xC1h) for which
FM3580 issues an
“
ACK
”
pulse.
The system now re-issues a
START condition, followed by Device address byte with Read-
Write bit set to “1”.
On receiving a valid device address FM3580
issues an
“
ACK
”
pulse. Now the FM3580 is ready to readout the
Seed Data. FM3580 first provides Byte-count byte (0x08h) indicat-
ing 8 bytes of Seed data will be readout. On receiving the Byte-count
byte, the system issues an
“
ACK
”
pulse. After this FM3580 issues
8 bytes of Seed data. For each byte thus received, the system
issues an
“
ACK
”
pulse except for the 8th byte of Seed data for which
the system issues a
“
No ACK
”
pulse and issues a STOP condition
to terminate the read cycle. Refer Read Seed Number diagram.
Reading Security code
Reading the 64-bit Security code is performed the same way as
reading the 64-bit Seed number but with the following difference:
instead of issuing by Read Seed number command byte (0xC1h),
Read Security code command byte (0xC3h) should be issued.
Refer Read Security code diagram.
Of the 64-bit Security code,
the first bit is always “1” and should be ignored. The next
63bits represent actual security code.
SMBus timeout
FM3580 will timeout and reset itself during any cycle whenever it
detects the LOW period of the SCL clock is more than 25ms. This
is in compliance to SMBus specification. After the timeout, any new
command to FM3580 should begin with a new START condition.
See tTIMEOUT specification under AC characteristics table.
SMBus Clock Stretching
Whenever a write command is issued (VID and Seed Number
writes), FM3580 will stretch the SCL clock LOW soon after the
STOP condition is detected at the end of write command cycle.
This clock stretching continues until the internal write is complete
(duration of tWP). See
“
Clock Stretching Diagram
”
.
SMBus Command compliance
Following table summarises FM3580 commands that are compli-
ant to SMBus/IIC commands.
Commands
Compliant to
Write Seed number
SMBus (Block Write Command)
Read Seed number
SMBus (Block Read Command)
Read Security code
SMBus (Block Read Command)
Write VID Register
SMBus (Send Byte Command)
Read VID Registers
IIC Bus (Sequential Read Command)