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參數(shù)資料
| 型號： | FMS3810KRC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DAC |
| 英文描述： | Triple Video D/A Converters 3 x 8 bit, 150 Ms/s |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 168K |
| 代理商： | FMS3810KRC |
FMS3810/3815
PRODUCT SPECIFICATION
4
REV. 1.08 12/21/00
Pin Descriptions
Pin
Name
Clock and Pixel I/O
CLK
Pin Number
LQFP
Value
Pin Function Description
26
TTL
Clock Input.
registered on the rising edge of CLK. It is recommended that CLK be
driven by a dedicated TTL buffer to avoid reflection induced jitter,
overshoot, and undershoot.
Red, Green, and Blue Pixel Inputs.
are registered on the rising edge of CLK.
The clock input is TTL-compatible and all pixel data is
R
G
B
Controls
SYNC
7-0
7-0
7-0
47-40
9-2
23-16
TTL
TTL-compatible RGB digital inputs
11
TTL
Sync Pulse Input.
current source which forms a sync pulse on any D/A converter output
connected to IO
S
. SYNC is registered on the rising edge of CLK along
with pixel data and has the same pipeline latency as BLANK and pixel
data. SYNC does not override any other data and should be used only
during the blanking interval. If the system does not require sync pulses,
SYNC and IO
S
should be connected to GND.
Blanking Input.
When BLANK is LOW, pixel inputs are ignored and the
D/A converter outputs are driven to the blanking level. BLANK is
registered on the rising edge of CLK and has the same two-pipe latency
as SYNC and Data.
Bringing SYNC LOW, turns off a 40 IRE (7.62 mA)
BLANK
10
TTL
Video Outputs
IO
R
IO
G
IO
B
33
32
29
0.714 V
p-p
Red, Green, and Blue Current Outputs.
drive RS-343A/SMPTE-170M compatible levels into doubly-terminated
75 Ohm lines. Sync pulses may be added to the green output.
When SYNC is HIGH, the current added to I
Current source outputs can
OG
is:
IO
S
= 3.64 (V
REF
/ R
REF
)
Voltage Reference
V
REF
35
+1.235 V
Voltage Reference Input/Output.
available on this pin. An external +1.235 Volt reference may be applied to
this pin to override the internal reference. Decoupling V
a 0.1μF ceramic capacitor is required.
Current-setting Resistor.
Full-scale output current of each D/A
converter is determined by the value of the resistor connected between
R
REF
and GND. Nominal value of R
REF
Internal 1.235V voltage reference is
REF
to GND with
R
REF
36
590
is found from:
R
REF
= 9.1 (V
REF
/I
FS
)
where I
D/A converter (without sync). Sync is 0.4 I
FS
is the full-scale (white) output current (amps) from the
FS
.
D/A full-scale (white) current may also be calculated from:
I
FS
= V
FS
/R
L
Where V
(ohms) on each D/A converter. V
Compensation Capacitor.
connected between COMP and V
FS
is the white voltage level and R
L
is the total resistive load
is the blank to full-scale voltage.
A 0.1 μF ceramic capacitor should be
DD
to stabilize internal bias circuitry.
FS
COMP
34
0.1 μF
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| FMS3810KRCT | 功能描述:數(shù)模轉換器- DAC 100Mhz D/a Converter 8Bit Tripple Video RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| FMS-38141-E | 制造商:GC Electronics 功能描述: |
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| FMS3818 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:PCB Layout Considerations for Video Filter / Drivers |
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