參數(shù)資料
型號(hào): FMS6501
廠(chǎng)商: Fairchild Semiconductor Corporation
英文描述: 12 Input 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers
中文描述: 12輸入9輸出與輸入鉗位,偏置電路的輸入和輸出視頻開(kāi)關(guān)矩陣驅(qū)動(dòng)
文件頁(yè)數(shù): 7/16頁(yè)
文件大?。?/td> 166K
代理商: FMS6501
7
www.fairchildsemi.com
FMS6501 Rev. 1A
F
I
2
C Interface
Operation
The I
2
C compatible interface conforms to the I
2
C spec for
Standard Mode. Individual addresses may be written. There
is no read capability. The interface consists of two lines.
These are a serial data line (SDA) and a serial clock line
(SCL). Both lines must be connected to a positive supply
through an external resistor. Data transfer may be initiated
only when the bus is not busy.
Figure 2: Bit Transfer
Bit Transfer
One data bit is transferred during each clock pulse. The data
on the SDA line must remain stable during the HIGH period of
the clock pulse. Changes in the data line during this time will
be interpreted as a control signal.
Data line
stable;
data valid
SCL
SDA
Change
of data
allowed
Start and Stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is
HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line, while the clock is HIGH is defined as the
stop condition (P).
Figure 3: Definition of START and STOP conditions.
S
P
START condition
STOP condition
SCL
SDA
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