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參數(shù)資料
| 型號(hào)： | FMS6502MTC24X |
| 廠商： | Fairchild Semiconductor |
| 文件頁(yè)數(shù)： | 11/13頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO SWITCH 8IN/6OUT 24TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 視頻交叉點(diǎn)開關(guān) |
| 電路： | 1 x 8:6 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 3.135 V ~ 5.25 V |
| 電流 - 電源： | 55mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁(yè)面： | 1214 (CN2011-ZH PDF) |
| 其它名稱： | FMS6502MTC24XDKR |
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FMS6502
8-Input,
6-Output
V
ideo
Switch
Matrix
with
Output
Drivers,
Input
Cl
amp,
and
Bias
Circuitry
2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6502 Rev. 1.0.0
7
I2C Interface
Figure 4.
Bit Transfer
Operation
The I2C-compatible interface conforms to the I2C specifi-
cation for Standard Mode. Individual addresses may be
written, but there is no read capability. The interface con-
sists of two lines: a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a posi-
tive supply through an external resistor. Data transfer
may be initiated only when the bus is not busy.
Bit Transfer
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the
HIGH period of the clock pulse. Changes in the data line
during this time are interpreted as control signals.
Data line
stable;
data valid
SCL
SDA
Change
of data
allowed
Start and Stop conditions
Both data and clock lines remain HIGH when the bus is
not busy. A HIGH-to-LOW transition of the data line,
while the clock is HIGH, is defined as start condition (S).
A LOW-to-HIGH transition of the data line, while the
clock is HIGH, is defined as stop condition (P).
Figure 5. START and STOP conditions
SP
START condition
STOP condition
SCL
SDA
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