參數(shù)資料
型號： FMS7401LEN
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： Digital Power Controller
中文描述： 8-BIT, EEPROM, 2.04 MHz, MICROCONTROLLER, PDIP8
封裝： PLASTIC, DIP-8
文件頁數(shù)： 25/80頁
文件大小： 1535K
代理商： FMS7401LEN
PRODUCT SPECIFICATION
FMS7401/7401L
REV. 1.0.2 6/23/04
25
5
Programmable Comparator Circuit
The Programmable Comparator circuit is an analog comparator whose outputs may be monitored by software or fed into a dig-
ital delay filter used to disable the PWM Timer 1 circuit or its PWM cycle. The comparator’s non-inverting input is software
selectable by the COMPSEL bit of the ADCNTRL2 register.
1
If COMPSEL=0, the non-inverting input of the Programmable
Comparator is the G4/AIN0 device pin. If COMPSEL=1, the non-inverting input of the Programmable Comparator is the G2/
AIN2 device pin. Before enabling the Programmable Comparator circuit, the selected analog input port pin must be configured
as a tri-state input bypassing the I/O circuitry.
2
The inverting input of the comparator is controlled by the Voltage Loop
(VLOOP) enable bit of the comparator control (COMP) register. If VLOOP=0, the voltage loop is disabled and the inverting
input of the analog comparator is configured as one of the 63 programmable voltage levels (V
THL
, V
THU
). If VLOOP=1, the
analog comparator is set in a voltage loop configuration with the Uncommitted (Error) Amplifier output (A
OUT
) connected to
the comparator’s inverting input (see
Figure 9
).
The Programmable Comparator circuit may be configured and controlled by software through the two 8-bit Comparator
Control (COMP) and Digital Delay (DDELAY) registers. Both the Programmable Comparator and the digital delay filter
must be enabled by software by setting the Comparator Enable (COMPEN) and clearing the EPWM bits of the Digital Delay
(DDELAY) register. Upon a system reset, the Programmable Comparator is disabled and the digital delay filter is enabled.
The COMP circuit is automatically disabled during Halt Mode. After exiting the Halt Mode, software must wait at least 10
instruction clock cycles before reading the COUT bit to ensure that the internal circuit has stabilized.
Table 8. Programmable Comparator (COMP) Control Register Bit Definitions
5.1
The Programmable Comparator circuit is configured to compare the G4/AIN0 or G2/AIN2 non-inverting input against the pro-
grammable voltage threshold levels on its inverting input (see
Table 9
and
Table 10
). The comparator output (C
OUT
) is 1 when
the G4/AIN0 or G2/AIN2 input pin rises above the selected voltage threshold. As long as the input stays above the selected
voltage threshold, the C
OUT
signal will hold its state. The C
OUT
signal will equal zero if the G4/AIN0 or G2/AIN2 input voltage
falls below the programmed threshold voltage or if the Programmable Comparator circuit is disabled. Software may change the
programmed threshold voltage on-the-fly as needed in the application. If the digital delay filter circuit is enabled (EPWM=0),
the C
OUT
signal is monitored for its rising edge to generate the PWMOFF signal. Refer to
Figure 8
and the following
Digital
Delay Filter with PWMOFF Output
section for addition details.
Programmable Comparator’s Voltage Threshold Levels (VLOOP=0)
Bit 6 of the ADCNTRL2 register is the Programmable Comparator non-inverting input selection (COMPSEL) bit.
1
If
COMPSEL=0, the non-inverting input of the Programmable Comparator is the G4/AIN0 device pin. If COMPSEL=1, the non-
inverting input of the Programmable Comparator is the G2/AIN2 device pin. Before enabling the Programmable Comparator
circuit, the selected analog input port pin must be configured as a tri-state input bypassing the I/O circuitry.
2
COMP Register (addr. 0xA0)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CL[5:0]
VLOOP
COUT
Bit
Description
CL[5:0]
Programmable Comparator Voltage Reference Level bits. Refer to
Table 9
and
Table 10
for details.
VLOOP
(0) Configures the inverting input of the analog comparator as one of the 63 programmable voltage levels (V
THL
, V
THU
).
(1) Configures the analog comparator in a voltage loop configuration with the Uncommitted Amplifier output (A
OUT
)
connected to the inverting input.
COUT
(0) G2/AIN2 or G4/AIN0 non-inverting input is less than inverting input configured by VLOOP.
(1) G2/AIN2 or G4/AIN0 non-inverting input is greater than inverting input configured by VLOOP.
相關(guān)PDF資料
PDF描述
FMS7401LEN14 Digital Power Controller
FMS7401LVN Digital Power Controller
FMS7401LVN14 Digital Power Controller
FMS7G10US60S SWTCH ROLLER SPDT 20A SCRW TERM
FMS7G10US60 SWTCH ROLLER SPDT 20A SOLD TERM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FMS7401LEN14 功能描述:處理器 - 專門應(yīng)用 Int Controller for Ballast RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
FMS7401LEN14_Q 功能描述:處理器 - 專門應(yīng)用 Int Controller for Ballast RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
FMS7401LVN 功能描述:處理器 - 專門應(yīng)用 Int Controller for Ballast RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
FMS7401LVN14 功能描述:8位微控制器 -MCU Int Controller for Ballast RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
FMS7401LVN14_Q 功能描述:8位微控制器 -MCU Int Controller for Ballast RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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