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參數(shù)資料
| 型號： | FMS988AKAC100 |
| 英文描述： | Signal Conditioner |
| 中文描述： | 信號調(diào)理 |
| 文件頁數(shù)： | 18/29頁 |
| 文件大?。?/td> | 481K |
| 代理商： | FMS988AKAC100 |
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PRODUCT SPECIFICATION
FMS9875
18
REV. 1.2.15 1/14/02
Figure 17.
50% Timeout
HSIN
COAST
HSOUT
Trailing edge terminates HSOUT
Timing Generator
Timing and Control logic generates:
1.
Internal sampling clock, SCK.
2.
Output data clocks, DCK and DCK.
3.
Output horizontal sync, HS
OUT
.
Internal clamp pulse, ICLAMP.
4.
With HSPOL set correctly, ICLAMP delay follows the trail-
ing edge of horizontal sync in (HSIN). Delay is set by the
CD register. Width of ICLAMP is set by the CW register.
Range of CD and CW values is 1–255 pixels.
Sync Stripper
Some video signals include embedded composite sync rather
than separate horizontal and vertical sync signals, typically
sync on green. Composite sync is extracted from Composite
Video at the ACS
IN
pin.
When the ACS
IN
signal falls below a 150mV ground refer-
enced threshold, sync is detected. Composite Sync Output,
DCS
OUT
reflects the ACS
IN
sync timing with non-inverted
CMOS digital levels.
Power Down
PWRDN = L minimizes FMS9875 power consumption.
Data outputs become high impedance. Clocks generation is
stopped. Register contents are retained. Sync stripping and
the internal voltage reference function.
Serial Interface
Register access is via a 2-wire I
2
C/SMBus compatible inter-
face. As a slave device, the 7-bit address is selected by the
A
1-0
pins (see Table 10). Serial port pins SDA and SCL com-
municate with the host SMBus/I
2
C controller which act as a
master.
Since the serial control port is design to interface with 3.3V
logic, the pins must be protected, if SDA and SCL signals
originate from 5V logic. Series connected 150
resistors are
recommended. (See Applications Section)
Table 10. Serial Interface Address Codes
Two signals comprise the bus: clock (SCL) and bi-directional
data (SDA). When receiving and transmitting data through
the serial interface, the FMS9875 acts as a slave, responding
only to commands by the I
2
C/SMBus master.
Data received or transmitted on the SDA line must be stable
for the duration of the positive-going SCL pulse. Data on
SDA may change only when SCL = L. An SDA transition
while SCL = H is interpreted as a start or stop signal.
A
1-0
00
01
10
11
7-Bit Address
4C
4D
4E
4F
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