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參數(shù)資料
| 型號(hào)： | FN3000-810-830 |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, DMA37 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 702K |
| 代理商： | FN3000-810-830 |
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201 McLean Blvd, Paterson, NJ 07504 Tel: (973) 881-8800 Fax: (973) 881-8361
E-mail: sales@synergymwave.com Web Site: http://www.synergymwave.com
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Figure 3: FN3000 frequency-information bitmap.
The binary equivalent of the integer part is to be loaded into registers R52 and R51. The binary equivalent of the
decimal part is to be loaded into registers R50, R43, R42, R41, and R40. Registers R53 down to R50 are to be loaded
first, followed by address 05h, and then registers R43 down to R40, followed by address 04h. Then the registers at 03h
and 09h can be loaded. The access to address 00000100 (04h) causes the internal loading of the fractional-division
number.
To facilitate rapid frequency changes after initialization, only the two packets that convey frequency information—
those addressed to 05h and 04h—need be sent to the synthesizer, in that order.
4. Timing Requirements
Figure 4 shows the corresponding timing diagram for the three-wire serial interface. The data is clocked on the rising
edge of each clock pulse.
Figure 4: Timing diagram for the FN3000 serial interface.
The following timing conditions apply to the FN3000 serial interface:
Clock pulse width: 10 ns (minimum)
Data set-up time: 5 ns (minimum)
Data hold time: 5 ns (minimum)
Strobe pulse width: 15 ns (minimum)
Figure 2: Data format for one address location.
The 56-bit representation of M is mapped across the data loaded into the 04h and 05h address spaces as shown in
Figure 3.
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