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參數(shù)資料
| 型號： | FN4117A |
| 廠商： | LINEAR INTEGRATED SYSTEMS INC |
| 元件分類： | 小信號晶體管 |
| 英文描述： | ULTRA-HIGH INPUT IMPEDANCE N-CHANNEL JFET |
| 中文描述： | N-CHANNEL, Si, SMALL SIGNAL, JFET, TO-72 |
| 封裝： | ROHS COMPLIANT, METAL PACKAGE-4 |
| 文件頁數(shù)： | 1/1頁 |
| 文件大?。?/td> | 14K |
| 代理商： | FN4117A |
Linear Integrated Systems
Linear Integrated Systems
4042 Clipper Ct., Fremont, CA 94538 TEL: (510) 490-9160 FAX: (510) 353-0261
ULTRA-HIGH INPUT IMPEDANCE
N-CHANNEL JFET
LS4117, 4118, 4119
FEATURES
LOW POWER
MINIMUM CIRCUIT LOADING
ABSOLUTE MAXIMUM RATINGS (NOTE 1)
@ 25
°
C (unless otherwise noted)
Gate-Source or Gate-Drain Voltage
(NOTE 1)
Gate-Current
Total Device Dissipation
(Derate 2mW/
°
C to 175
°
C)
Storage Temperature Range
Lead Temperature
(1/16" from case for 10 seconds)
I
DSS
<90
μ
A (2N4117)
I
GSS
<1 pA (2N4117A Series)
-40V
50mA
300mW
-65
°
C to +175
°
C
255
°
C
ELECTRICAL CHARACTERISTICS @ 25
°
C (unless otherwise noted)
2N4117/A
FN4117/A
2N4118
2N4118A
2N4119
2N4119A
SYMBOL CHARACTERISTICS MIN MAX MIN MAX MIN MAX UNITS CONDITIONS
I
GSS
Standard only
--
-25
I
GSS
"A" Series only
--
-2.5
BV
GSS
V
GS(off)
I
DSS
(NOTE 2)
FN4117/A 0.015
g
fs
Transconductance
(NOTE 2)
g
os
Conductance
C
iss
Capacitance
C
rss
Transfer Capacitance
Gate Reverse Current
--
-10
--
--
--
--
-10
-25
-1
-2.5
--
--
--
--
--
-10
-25
-1
-2.5
--
pA
nA
pA
nA
V
GS
= -20V V
DS
= 0
Gate Reverse Current
--
-1
V
GS
=-20V V
DS
= 0
Gate-Source Breakdown Voltage
-40
--
-40
-40
I
G
=-1
μ
A
V
DS
=10V
V
DS
=10V
V
DS
= 0
I
D
= 1nA
V
GS
= 0
Gate-Source Cutoff Voltage
-0.6
-1.8
-1
-3
-2
-6
Saturation Drain Current
0.03
0.09
0.08
0.24
0.20
0.60
mA
Common-Source Forward
70
210
80
250
100
330
Common-Source Output
--
3
--
5
--
10
Common-Source Input
--
3
--
3
--
3
V
DS
= 10V V
GS
= 0
Common-Source Reverse
--
1.5
--
1.5
--
1.5
150
°
C
150
°
C
V
μ
mho
pF
f=1MHz
f=1kHz
NOTES:
1. Due to symmetrical geometry, these units may be operated with source and drain leads interchanged.
2. This parameter is measured during a 2 ms interval 100 ms after power is applied. (Not a JEDEC condition.)
1
2
3
4
Case
G
G
D
S
S
TO-72
Bottom View
D
C
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