參數(shù)資料
型號: FOD8012R2
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO8
封裝: LEAD FREE, SOP-8
文件頁數(shù): 7/12頁
文件大?。?/td> 207K
代理商: FOD8012R2
2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FOD8012 Rev. 1.0.5
4
FOD8012
High
CMR,
Bi-Directional,
Logic
Gate
Optocoupler
Switching Characteristics
TA = -40C to +110C, 3.0V ≤ VDD ≤ 5.5V, unless otherwise specified.
Apply over all recommended conditions, typical value is measured at VDD1 = VDD2 = +3.3V, TA=25C
Notes:
1. No derating required.
2. 0.1F bypass capacitor must be connected between Pin 1 and 4, and 5 and 8. The capacitors should be kept close
to the supply pins.
3. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted
together.
4. 3,750 VACRMS for 1 minute duration is equivalent to 4,500 VACRMS for 1 second duration.
5. PWD is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen for one channel
switching, while holding the other channel output at a low or high state, or while both channels are in synchronous
data transmission mode.
6. tPSK(CC) is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between the two
channels within a single device.
7. tPSK(PP) is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between any two
units from the same manufacturing date code that are operated at same case temperature, at same operating
conditions, with equal loads.
8. Common mode transient immunity at output high is the maximum tolerable positive dVcm/dt on the leading edge of
the common mode impulse signal, Vcm, to assure that the output will remain high. Common mode transient
immunity at output low is the maximum tolerable negative dVcm/dt on the trailing edge of the common pulse signal,
Vcm, to assure that the output will remain low.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Data Rate
15
Mbit/s
tPHL
Propagation Delay Time
to Logic Low Output
PW = 66.7ns, CL = 15pF
37
60
ns
tPLH
Propagation Delay Time
to Logic High Output
PW = 66.7ns, CL = 15pF
40
60
ns
PWD
Pulse Width Distortion,
| tPHL – tPLH |
PW = 66.7ns, CL = 15pF
(5)
315
ns
tPSK(CC)
Channel-Channel Skew
PW = 66.7ns, CL = 15pF
(6)
12
25
ns
tPSK(PP)
Part-Part Skew
PW = 66.7ns, CL = 15pF
(7)
30
ns
tR
Output Rise Time
(10% to 90%)
PW = 66.7ns, CL = 15pF
6.5
ns
tF
Output Fall Time
(90% to 10%)
PW = 66.7ns, CL = 15pF
6.5
ns
|CMH|
Common Mode Transient
Immunity at Output High
VI = VDD1, VO > 0.8VDD1,
VCM = 1000V
(8)
20
40
kV/s
|CML|
Common Mode Transient
Immunity at Output Low
VI = 0V, VO < 0.8V,
VCM = 1000V
(8)
20
40
kV/s
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