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參數(shù)資料
| 型號(hào)： | FRAME-IT-1 |
| 英文描述： | Frame-It-1 Deinterlacer Product Brief |
| 中文描述： | 幀它- 1去隔行掃描產(chǎn)品簡(jiǎn)介 |
| 文件頁(yè)數(shù)： | 1/2頁(yè) |
| 文件大?。?/td> | 79K |
| 代理商： | FRAME-IT-1 |
Product Brief
Tel 408.919.4111
Fax 408.919.4122
www.zoran.com
10
/02-LDI
Zoran’s
Frame-It-1 Video Deinterlacer is a silicon-efficient,
high-performance Intellectual Property Core for video IC designs
requiring progressive video output. Frame-It-1 is based on Zoran’s
extensive experience delivering high quality, high volume video ICs
to major consumer products manufacturers worldwide. Frame-It-1
employs a robust motion detection and an intelligent interpolation
algorithm in a easily implemented, fully synchronous design. 3:2
pulldown, 2:2 pulldown, and bad edit detection enable superior dein-
terlacing of source material orginally from film.
Proven in silicon, the Frame-It-1 Video Deinterlacer greatly reduces
the risk and time involved when integrating the video deinterlacing
function into an IC. Expensive, discrete components can be elimi-
nated from system designs. Frame-It-1 is designed into Zoran's
Vaddis family of DVD decoders, which are in mass production and
are used in brand name consumer products worldwide.
VIP-II Demonstration System
The VIP-II is an FPGA demonstration system for Zoran's IP Core
products. The VIP-II accepts composite video, S-video and compo-
nent video inputs and with its user friendly GUI
,
enables customers
to thoroughly evaluate the performance of Zoran's IP Core products.
Features
"I to P" converter
Converts interlaced video to progressive output video
Robust motion detection based algorithm
Weaves still areas of the image
Advanced interpolation for moving areas of the image
3:2 and 2:2 pulldown detection for film modes
Bad edit detection
Silicon efficient design
Requires only a single clock input from 20 to 30 MHz
Fully synchronous design
Process technology independent "softcore"
Zoran Corporation
3112 Scott Boulevard
Santa Clara, CA 95054-3317
Frame-It-1-PB-1.0
Frame-It-1
TM
Video Deinterlacer
Intellectual Property Core
Solutions on a chip for enjoying the digital life style
Integrated Circuit Applications
LCD controllers
LCD-TV
PDP-TV
Projector TV Systems
Progressive output CRT-TV
Any IC requiring progressive video output
Description
Deliverables
Compilable Verilog source code
Bit-accurate, cycle-accurate C++ model
Synopsis synthesis scripts
Test input files
Documentation
VIP-II FPGA demonstration system available
Interlaced Video
Input
Line
Buffers
Optional
Line
Buffers
Field Buffer
Control
Field
Buffers
Input
Control
Motion
Detector
Gradient
Detector
Adaptive
Bob-
Weave
Output
Control
Deinterlaced Video
Output
Frame-It-1
Video Deinterlacer
Frame-It-1 Video Deinterlacer Block Diagram
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