參數(shù)資料
型號(hào)： FS450
廠商： Electronic Theatre Controls, Inc.
英文描述： i-Net TV Interface Video Processor
中文描述： 一至網(wǎng)絡(luò)電視接口視頻處理器
文件頁(yè)數(shù)： 57/60頁(yè)
文件大?。?/td> 266K
代理商： FS450
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
JUNE, 2000, VERSION 1.2
57
COPYRIGHT
ó
1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
8.3 Switching Characteristics
Parameter
Clocks
fCKIN
TV Encoder Reference Clock Frequency
fXTOL
TV Reference Clock Frequency Tolerance
tPWHT
TV Reference Clock Pulse Width, HIGH
tPWLT
TV Reference Clock Pulse Width, LOW
fPCKIN
VGA Clock Positive Edge Frequency
fNCKIN
VGA Clock Negative Edge Frequency
fCORE
VGA Core Frequency
4
fVCKO
VGA Clock Output
tJIT-VCK VGA Clock Output Jitter (peak-to-peak)
fPLLREFPLL Reference Clock Frequency
M
PLL Numerator
tPWHV
VGA Clock Positive Edge Pulse Width, HIGH
tPWLV
VGA Clock Negative Edge Pulse Width, LOW
Reset
Assert fCKIN cycles on RESET\ to reset the part
Digital RGB Input Port
tPDH
VGA_PCKIN to Data Hold Time
tNDH
VGA_NCKIN to Data Hold Time
tPSU
VGA_PCKIN to Data Setup Time
tNSU
VGA_NCKIN to Data Setup Time
CCIR 656 Video Input and Output Port
tTDH
TV_CKIN to Data Hold Time
tTSU
TV_CKIN to Data Setup Time
tTDO
TV_CKIN to Data Out Delay
Serial Microprocessor Interface
tDAL
SCL Pulse Width, LOW
tDAH
SCL Pulse Width, HIGH
tSTAH
SDA Start Hold Time
tSTASU
SCL to SDA Setup Time (Stop)
tSTOSU SCL to SDA Setup Time (Start)
tBUFF
SDA Stop Hold Time Setup
tDSU
SDA to SCL Data Setup Time
tDHO
SDA to SCL Data Hold Time
Conditions
Min
Typ
2
Max
Unit
27.0
30
MHz
ppm
ns
ns
MHz
MHz
MHz
MHz
ps
kHz
50
3
15.0
15.0
27.0
27.0
40/60 duty cycle
40/60 duty cycle
85.0
85.0
50.0
85.0
200
100
1200
27.0
over a cycle
24
500
5.0
5.0
16
Clocks
0
0
ns
ns
ns
ns
1.5
1.5
0
ns
ns
ns
10.0
24.0
1.3
0.6
0.6
0.6
0.6
1.3
300
300
μs
μs
μs
μs
μs
μs
ns
ns
Notes:
1. GTL outputs are open drain, intended to drive 31 ohm termination from 1.8 volts.
2. Values shown in Typ column are typical for VDD = +3.3V and TA = 25°C
3. TV subcarrier acceptance band is
±
300 Hz.
4. VGA Core Frequency = VGA Clock Frequency/(UIM_DEC+1)
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