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參數(shù)資料
| 型號： | FS451 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | i-Net TV Interface Video Processor |
| 中文描述： | 一至網(wǎng)絡(luò)電視接口視頻處理器 |
| 文件頁數(shù)： | 34/60頁 |
| 文件大?。?/td> | 266K |
| 代理商： | FS451 |
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FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
JUNE, 2000, VERSION 1.2
34
COPYRIGHT
ó
1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
6.2.14 MISC - Miscellaneous Bits 34, 35 Register
Miscellaneous Bits Register (34)
7
6
5
4
3
2
1
0
0
0
NCO_LOAD
1
NCO_LOAD
0
0
0
0
0
Miscellaneous Bits Register (35)
7
6
5
4
3
2
1
0
GTLIO_PD
0
0
0
0
0
VGACKDIV
0
Reg
Bit#
Bit Name
Description
34
5,4
NCO_LOAD
1-0
NCO Load Control Bits.
The PLL M and N dividers and the
NCO Numerator (NCON) and denominator (NCOD) share the
same address (separate memory). The NCO Load Control bits
determine which registers are loaded when the NCON and
NCOD registers are written (see table below). M uses the lower
11 bits of NCON, and N uses the lower 11 bits of NCOD.
35
1
VGACKDIV
VGA Clock Divide.
Setting this bit divides the internal clock by
2 when the VGA input is in decimation (for XGA) mode.
35
7
GTLIO_PD
GTL I/O Power Down.
Setting this bit puts all the GTL pins
into power down mode.
Notes:
NCO_LOAD
0
1
2
Meaning
Load NCO Numerator and Denominator only.
Load M and N PLL Dividers only.
Load NCO Numerator and Denominator and
set M=512, N=128.
Load M and N PLL Dividers and set NCO
Numerator and Denominator both to 50.
3
Table 5: NCO_LOAD Control Bits
1) M is loaded with the desired value -2
2) N is loaded with the desired value -1
3) Using the 24 bit NCON and NCOD yields a very fine frequency resolution of 1.5 Hz but dithers the clock.
The speed of the clock dither is sufficiently limited by the narrowband (around 5 kHz) PLL to prevent any
problem with data transfers to the FS450. In fact, it provides an advantage for passing EMI certification
and behaves much like off the shelf dithered clocks designed specifically for that purpose.
4) Using the 11 bit M/N ratio gives a frequency resolution of 13 kHz, but it has no dithering. This is ideal for
dual VGA monitor and TV applications. Dithering the clock to a VGA controller makes the lines wiggle on
the connected VGA monitor, making it difficult to read. This however limits the scaling possibilities, and
close attention has to be paid to the factors of the VGA/TV pixels and lines so that they cancel down to 11
bit M and N numbers.
5) Both M/N and Numerator/Denominator can be used together, to generate a compromise performance.
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