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參數(shù)資料
| 型號： | FS6131-01 |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 27 MHz, PDSO16 |
| 封裝： | 0.150 INCH, SOP-16 |
| 文件頁數(shù)： | 34/40頁 |
| 文件大?。?/td> | 746K |
| 代理商： | FS6131-01 |
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4
AMI Semiconductor - Rev. 2.0, Jun. 05
www.amis.com
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
To understand the operation, refer to Figure 3. The M-counter (with a modulus of M) is cascaded with the dual-modulus pre-scaler. If the prescaler
modulus were fixed at N, the overall modulus of the feedback divider chain would be MXN. However, the A-counter causes the pre-scaler modulus
to be altered to N+1 for the first A outputs of the pre-scaler. The A-counter then causes the dual-modulus prescaler to revert to a modulus of N
until the M-counter reaches its terminal state and resets the entire divider. The overall modulus can be expressed as
)
(
)
1
(
A
M
N
A
-
+
where M
A, which simplifies to
A
N
M
+
4.1.3 Feedback Divider Programming
The requirement that M
A means that the feedback divider can only be programmed for certain values below a divider modulus of 56. The
selection of divider values is listed in Table 2.
If the desired feedback divider is less than 56, find the divider value in the table. Follow the column up to find the A-counter program value. Follow
the row to the left to find the M-counter value.
Above a modulus of 56, the feedback divider can be programmed to any value up to 16383. See both Table 3 and Table 8 for additional
programming information.
Table 2: Feedback Modulus Below 56
M-Counter:
FBKDIV[13:1]
A-Counter; FBKDIV[2:0]
000
001
010
011
100
101
110
111
00000000001
8
9
-
00000000010
16
17
18
-
00000000011
24
25
26
27
-
00000000100
32
33
34
35
36
-
00000000101
40
41
42
43
44
45
-
00000000110
48
49
50
51
52
53
54
-
00000000111
56
57
58
59
60
61
62
63
Feedback Divider Modulus
4.1.4 Post Divider
The post divider consists of three individually programmable dividers, as shown in Figure 4.
Post
Divider 1
(N
P1)
Post
Divider 2
(N
P2)
Post
Divider 3
(N
P3)
POST3[1:0]
POST2[1:0]
POST1[1:0]
POST DIVIDER (N
Px)
f
out
f
GBL
Figure 4: Post Divider
The moduli of the individual dividers are denoted as NP1, NP2 and NP3, and together they make up the array modulus NPx.
3
2
1
P
Px
N
=
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| FS6131-01G | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Programmable Line Lock Clock Generator IC |
| FS6131-01G-XTD | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01G-XTP | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTD | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK (IND) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTP | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK IND RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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