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參數(shù)資料
| 型號： | FS6322-05 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Three-PLL Clock Generator IC |
| 中文描述： | 三PLL時鐘發(fā)生器芯片 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 59K |
| 代理商： | FS6322-05 |
AMERICAN MICROSYSTEMS, INC.
July 2000
5
7.11.00
FS6322-05
Three-PLL Clock Generator IC
Table 6: AC Timing Specifications
Unless otherwise stated, V
= 3.3V ± 10%, no load on any output, and ambient temperature range T
= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
±
3
σ
from typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK
(MHz)
MIN.
TYP.
MAX.
UNITS
Clock Output (CLK_X)
Duty Cycle *
Crystal oscillator derived outputs
Measured @1.4V; C
L
= 20pF
PLL derived outputs
Measured @1.4V; C
L
= 20pF
V
O
= 0.4V to 2.4V; C
L
= 20pF
V
O
= 2.4V to 0.4V; C
L
= 20pF
From rising edge to next rising edge at V
DD
/2, C
L
=
20pF
43
51
57
%
Duty Cycle *
45
51
55
%
Rise Time *
Fall Time *
t
r
t
f
2.2
1.8
ns
ns
Jitter, Period (RMS) *
t
j(1
σ
)
50
ps
Jitter, Period (peak-peak) *
t
j(
P)
From rising edge to next rising edge at V
DD
/2, C
L
=
20pF
400
ps
Jitter, Cumulative (RMS)*
t
j(LT)
PLL-derived outputs
From 0-500
μ
s at V
DD
/2, C
L
= 20pF
compared to ideal clock source
PLL derived outputs
@ 100KHz offset from fundamental
100
ps
Phase Noise *
-80
dbC/Hz
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