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參數(shù)資料
| 型號： | FS6322-08 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | THREE PLL CLOCK GENERATOR IC |
| 中文描述： | 三鎖相環(huán)時鐘發(fā)生器IC |
| 文件頁數(shù)： | 5/7頁 |
| 文件大小： | 62K |
| 代理商： | FS6322-08 |
AMERICAN MICROSYSTEMS, INC.
February 2001
5
2.2.01
Advance Information
FS6322-08
Three-PLL Clock Generator IC
Table 6: AC Timing Specifications
Unless otherwise stated, V
= 3.3V ± 10%, no load on any output, and ambient temperature range T
= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
±
3
σ
from typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK
(MHz)
MIN.
TYP.
MAX.
UNITS
Clock Output (CLK_X)
Duty Cycle *
Crystal oscillator derived outputs
Measured @1.4V; C
L
= 20pF
PLL derived outputs
Measured @1.4V; C
L
= 20pF
V
O
= 0.4V to 2.4V; C
L
= 20pF
V
O
= 2.4V to 0.4V; C
L
= 20pF
From rising edge to next rising edge at V
DD
/2, C
L
=
20pF
43
51
57
%
Duty Cycle *
45
51
55
%
Rise Time *
Fall Time *
t
r
t
f
ns
ns
Jitter, Period (RMS) *
t
j(1
σ
)
ps
Jitter, Period (peak-peak) *
t
j(
P)
From rising edge to next rising edge at V
DD
/2, C
L
=
20pF
ps
Jitter, Cumulative (RMS)*
t
j(LT)
PLL-derived outputs
From 0-500
μ
s at V
DD
/2, C
L
= 20pF
compared to ideal clock source
PLL derived outputs
@ 100KHz offset from fundamental
ps
Phase Noise *
dbC/Hz
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| FS6330 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN HUB CLOCK GENERATOR IC |
| FS6330-01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN HUB CLOCK GENERATOR IC |
| FS6370 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:EEPROM Programmable 3-PLL Clock Generator IC |
| FS6370-01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM Programmable 3-PLL Clock Generator IC |
| FS6370-01G-XTD | 功能描述:時鐘發(fā)生器及支持產品 EE PROG 3-PLL CLOCK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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