![](http://datasheet.mmic.net.cn/370000/FS6330_datasheet_16690032/FS6330_3.png)
AMERICAN MICROSYSTEMS, INC.
May 2000
5.23.00
3
Preliminary information
FS6330
LAN Hub Clock Generator IC
Table 5: DC Electrical Specifications
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range T
= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are
±
3
σ
from typical. Negative currents indicate current flows out of the device.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Overall
Supply Current, Dynamic, with Loaded
Outputs
I
DD
All 3.3V supplies = 3.465V
mA
X1 Crystal Oscillator Feedback
Threshold Bias Voltage
High-Level Input Current
V
TH
I
IH
0.5V
DD
32
V
μ
A
μ
A
V
IH
= 3.3V
Low-Level Input Current
I
IL
V
IL
= 0V
As seen by an external crystal connected
to XIN and XOUT
As seen by an external clock driver on
XOUT; XIN unconnected
-32
Crystal Loading Capacitance *
C
L(xtal)
13.5
18
22.5
pF
Input Loading Capacitance *
C
L(XIN)
36
pF
X2 Crystal Oscillator Drive
High Level Output Source Current
Low Level Output Sink Current
I
OH
I
OL
V
I
= 3.3V, V
O
= 0V
V
I
= 0V, V
O
= 3.3V
-8
9
mA
mA
Clock Outputs
High-Level Output Source Current
Low-Level Output Sink Current
Output Impedance
Short Circuit Output Source Current
Short Circuit Output Sink Current
I
OH
I
OL
z
O
I
OSH
I
OSL
V
O
= 2.4V
V
O
= 0.4V
Measured at 1.5V
V
O
= 0V; shorted for 30s, max.
V
O
= 3.3V; shorted for 30s, max.
mA
mA
mA
mA
Table 6: AC Timing Specifications
Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature T
= 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and
are not currently production tested to any specific limits. MIN and MAX characterization data are
±
3
σ
from typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Clock Outputs
Duty Cycle *
d
t
Ratio of high pulse width to one clock period,
measured at 1.5V
45
55
%
Clock Skew *
t
sk(o)
CLKB1 to CLKB4 at 1.5V
On rising edges 500
μ
s apart at 1.5V relative to an
ideal clock, C
L
=15pF, all PLLs active
From rising edge to rising edge at 1.5V, C
L
=15pF,
all PLLs active
250
ps
Jitter, Long Term (
σ
y
(
τ
)) *
t
j(LT)
ps
Jitter, Period (peak-peak) *
t
j(
P)
150
ps
Rise Time *
t
r
t
f
Measured @ 0.4V – 2.4V; C
L
=15pF
Measured @ 2.4V – 0.4V; C
L
=15pF
1.2
ns
Fall Time *
1.2
ns