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參數(shù)資料
| 型號(hào)： | FS8170 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 2.5 GHz Low Power Phase-locked Loop IC |
| 中文描述： | 2.5 GHz的低功耗鎖相環(huán)集成電路 |
| 文件頁(yè)數(shù)： | 6/17頁(yè) |
| 文件大?。?/td> | 269K |
| 代理商： | FS8170 |
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FS8170
Page 6
May 2003
Functional Description
Programmable Input Frequency Divider
The VCO output to the FIN pin is divided by the programmable divider and then inter-
nally output to the phase/frequency detector (PFD) as
f
V
. The programmable input fre-
quency divider consists of a multi-modulus (selectable ÷ 32/33 or ÷ 64/65
(M/M+1))
prescaler and a 18-bit N-counter, which is further comprised of a 7-bit swallow A-counter,
and a 11-bit main
B
-counter. The total divide ratio,
N
, is related to values for
M
,
A
, and
B
through the relation
with
M
64
The minimum programmable divisor for continuous counting is given by
, and is
for the ÷ 32/33 prescaler mode, and is
for the ÷ 64/65 mode. Hence, the valid total divide ratio range for
the input divider is
for the ÷ 32/33 mode and
the ÷ 64/65 mode.
for
Programmable Reference Frequency Divider
The crystal oscillator output is divided by the programmable reference divider and then
internally output to the PFD as
f
R
. The programmable reference frequency divider con-
sists of a 14-bit reference R-counter. Becasue of its specific design, the minimum accept-
able divisor for
R
is 3, and hence the total divide ratio,
R
, ranges from 3 to 16383.
Shift Register Configuration
The divide ratios for the input and reference dividers are input using a 19-bit serial inter-
face consisting of separate clock (CLK), data (DATA), and load enable (LE) lines. The
format of the serial data is shown in Table 1. The data on the DATA line is written to the
shift register on the rising edge of the CLK signal and is input with MSB first, and the last
bit is used as the latch select control bit. The data on the DATA line should be changed on
the falling edge of CLK, and LE should be held LOW while data is being written to the
shift register. Data is transferred from the shift register to one of the frequency divider
latches when LE is set HIGH. When the latch select control bit is set LOW, data is loaded
to the 18-bit
N
-counter latch, and when the latch select control bit is set HIGH, the 4
MSBs are recognized as CS, LDS, FC, SW, respectively, and the next 14 data bits are
loaded to the 14-bit
R
-counter latch. The definition of the 4 MSBs will be described in
Table 5 and 6. Note that LDS should be set LOW for normal operation.
Also, serial input data timing waveforms are shown in Fig. 1.
N
M
1
+
(
)
A
M
B
A
–
(
)
×
+
×
M
B
A
,
+
×
=
=
B
M
(
(
×
A
.
1
–
–
≥
)
1
×
32
32
1
–
(
)
×
992
=
64
)
4032
N
=
992 to 65631
=
N
4032 to 131135
=
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